AMD-761 Datasheet, PDF (169/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Table 23 is an example on how to size the Memory Base register
for a total of 320 Mbytes using one-bank DIMM at 64 Mbytes
per bank and a two-bank DIMM at 128 Mbytes per bank.
Table 23. Memory Sizing Example, 320 Mbytes Total
Registers – Bus:00 Device:00 Function:00
0 1 2 3 4 5 6 7 8 9 ABCDE F
C 83 03 00 10 00 00 00 00 83 07 00 00 83 07 00 08
D 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
3.4
3.4.1
DDR Memory DIMM Timings
One of the most important changes from earlier SDRAM DIMM
technology is that conservative settings for CAS Latency (CL)
are no longer valid—that is, when there is doubt that the
DIMM works using CL=2, falling back to a setting of CL=3 is
not an alternative as it was on single data rate devices.
CAS latency for a DIMM must be set to a value described in the
SPD on the DIMM. A DIMM that is set to something other than
a rated value in its SPD cannot be expected to work and most
likely will not work.
Industry standards for CL on DDR DIMMS are 1.5, 2.0, and 2.5.
Please notice that the AMD-761 system controller supports
CL=3.0 as the highest CL setting. Some legacy DDR devices
support CL=3.0, but most devices available today specify
CL=2.5 as a maximum. The AMD-761 system controller does
not support CL=1.5.
Memory Timings
The AMD-761 system controller supports the following DDR
device timing parameters: t_CL, t_RCD, t_RAS, t_RP, t_RC, t_RRD, t_WR,
and t_WTR. The t_CL, t_RCD, t_RAS, t_RP, t_RC, and t_RRD timings are
available from the SPD. The data format of each byte is
described in the application note published by IBM and other
sources. Matching this data to memory controller settings is a
function of speed of the memory bus. Examples of settings are
developed for bus speeds of 100 MHz and 133 MHz.
Chapter 3
DDR SDRAM Interface
157