AMD-761 Datasheet, PDF (177/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Table 27. System Related Timings
Name
0x0x0x54 Bit(s) Typical Setting Description
Page Hit Limit
15:14
10b
8 cycles
Idle Cycle Limit
18:16
001b
8 cycles
Registered DIMM Enable
0 for unbuffered
27
x
1 for registered
Read Wait State
28
1
Always set
Address Timing for Copy-B
29
0 for unbuffered
x
1 for registered
Address Timing for Copy-A
30
0 for unbuffered
x
1 for registered
Super Bypass Wait State
0 < 133 MHz
31
X
1 @ 133 MHz
3.6 DRAM Mode/Status Settings
Chip-Select Width
The AMD-761 system controller memory controller contains
additional DDR memory controller settings starting at (Dev
0:F0:0x58). These settings are: x4 DDR device symmetry
configuration, refresh control (which includes refresh rate,
refresh disable, and burst refresh enable), suspend to RAM
(STR) control, DDR device initialization control, and AMD-761
system controller DDR clock output control.
The SDRAM Chip-Select Width bits (Dev 0:F0:0x58, bits [7:0])
are used to indicate DDR device data widths installed for the
corresponding chip select. The AMD-761 system controller can
differentiate between x4 or x8/x16 banks by BIOS setting a
corresponding bit for the chip select in this register. A bit
should be set to 1b to represent a x4 bank or set to 0b to
represent a x8/x16 bank.
The x8 and X16 devices use one DQS data strobe per byte,
whereas a x4 device uses one DQS data strobe per nibble
(4-bit). Because the AMD-761 system controller DRAM
controller uses the data mask (DM) signals as DQS data strobes
during data transfers to x4 devices, the DRAM controller uses
these bits to determine the function for the DM signals. The
Chapter 3
DDR SDRAM Interface
165