AMD-761 Datasheet, PDF (9/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
AMD-761 System Controller Configuration Register
Bits Unknown at RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Settings for AMD Athlon Processor
SYSCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AMD-761 System Controller Socket2000 Memory Map . . . . . 10
AMD Athlon Processor Special Cycle Encodings . . . . . . . . . . . 12
I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device 0, Function 0 Configuration Register Map . . . . . . . . . . 27
AMD-761 System Controller SERR# Assertion Control
and Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Wait State Settings for DRAM Timing Register . . . . . . . . . . . . 55
I/O Pad Drive Strength and Input Type . . . . . . . . . . . . . . . . . . . 90
DDR Memory Base Address Register Locations . . . . . . . . . . . . 95
AMD-761 DRAM Addressing Modes . . . . . . . . . . . . . . . . . . . . . 96
Device 0, Function 1 Configuration Register Map . . . . . . . . . . 97
PDL Calibration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DDR PDL Configuration Register Locations. . . . . . . . . . . . . . 101
Device 1 Configuration Register Map . . . . . . . . . . . . . . . . . . . 117
AMD-761 System Controller Memory-Mapped Registers . . . 140
Typical CL Parameter Settings for PC1600 and PC2100 . . . . 151
DIMM Bank Address Bit Definition. . . . . . . . . . . . . . . . . . . . . 152
Memory Size Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Total Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
AMD-761 System Controller DDR SDRAM
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Memory Sizing Example, 128 Mbytes Total . . . . . . . . . . . . . . 156
Memory Sizing Example, 320 Mbytes Total . . . . . . . . . . . . . . 157
CAS Latency Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DDR Device Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Dev 0:F0:0x54 Bit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
System Related Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
List of Tables
9