AMD-761 Datasheet, PDF (108/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions
Bit Name
31–23 CS_Base
22–16 Reserved
15–7 CS_Mask
6–3 Reserved
2–1 Addr_Mode
0 CS_En
Memory Base Address Registers 0–7 (Dev0:F0:0xC0–0xDF)
Function
Chip-Select Base
This bit field defines which 8-Mbyte boundary the given bank services. Incoming
addresses are compared against field, subject to the mask field in bits [15:7].
Reserved
Chip-Select Mask
This bit field defines what bits in the address are ignored when incoming addresses are
compared to the CSBase in bits[31:23] above. If a given bit is set, the corresponding bit in
the compare is ignored.
Reserved
Addressing Mode
This bit field determines the addressing mode for this CS, based on the type of DIMM
installed, according to Table 11. This addressing applies to the physical addressing on the
MAA and MAB address buses. Note that modes 00 and 11 are reserved.
Chip-Select Enable
When set, this bank is eligible for selection by incoming addresses. When clear, this bank’s
chip select is not asserted and the values in [31:23] and [15:7] are ignored.
Programming Notes
Note that these registers are not initialized at reset time, but must be initialized by BIOS for proper operation. This action
should be done prior to attempting DRAM access. Table 11 shows DRAM addressing modes.
Table 11. AMD-761™ DRAM Addressing Modes
Mode
Pins 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mode 1
Row ^{12 11}
Addr_Mode = 01
64 Mbyte x4/8/16
Col
12
11
128 Mbyte x4/8/16
BK BK
24 23 22 21 20 19 18 17 16 15 14 13
27 PC 26 25 10 9 8 7 6 5 4 3
Mode 2
Row ^{12 11 25 24 23 22 21 20 19 18 17 16 15 14 13}
Addr_Mode = 10
256 Mbyte x4/8/16
Col
12
11 29 28 PC 27 26 10 9
8
7
6
5
4
3
512 Mbyte x4/8/16
BK BK
96
AMD-761™ System Controller Programmer’s Interface
Chapter 2