AMD-761 Datasheet, PDF (57/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31–16 Reserved
15-14 SERR_Enable
13 Reserved
12 ECC_Diag
11–10 ECC_Mode
9–8 ECC_Status
ECC Mode/Status (Dev0:F0:0x48)
Function
Reserved
System Error Enable
These bits control the AMD-761™ system controller’s reporting of ECC errors to the
system via the SERR# pin on the PCI bus. Note that SERR# assertion is still subject to the
normal PCI SERR# enable (bit 8 in Dev 0:F0:0x04). Refer to Table 7 on page 34 for
details about SERR# assertion and status.
00 = SERR# assertion is disabled.
X1 = Multiple bit errors force SERR# assertion.
1X = Single bit errors force SERR# assertion.
Reserved
Error Correcting Code Diagnostic Mode Enable
0 = ECC diagnostic mode disabled
1 = ECC diagnostic mode enabled
When the ECC diagnostic mode is enabled, the AMD-761 system controller always
writes 0x00 to the ECC byte to aid testing of the ECC logic. During partial writes, the
RMW sequence still occurs, but the ECC bits are always written to 0x00.
For reads, the ECC circuitry is unaffected by the ECC_Diag bit. The ECC code returned
from memory is checked, and errors are reported in the ECC_Status bits as usual.
Correction is not performed in this mode.
Error Correcting Code Mode
00 = ECC disabled, no error detection or correction is performed.
01 = EC_HiPerf mode enabled. Error checking and status reporting is enabled. Data
destined for the PCI/AGP and memory (RMR) is not corrected.
10 = ECC_HiPerf mode enabled. Error checking and status reporting is enabled. Data
destined for the PCI/AGP and memory (RMR) is corrected.
11 = ECC_Scrub mode enabled. Error checking and status reporting is enabled. Data
destined for the PCI/AGP and memory (RMR) is corrected. The memory
contents are corrected (scrubbed) after all reads with errors.
Error Correcting Code Status
This bit field indicates the status of the ECC detect logic as follows:
00 = No error
X1 = MED: multi-bit error detect
1X = SED: single-bit error detect
The ECC status bits and corresponding failing chip-select indicators are set by the first
error detected of each type (SED or MED). The AMD-761 system controller does not log
any new errors of each type or assert SERR# until software clears the associated
ECC_Status bit by writing a 1.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
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