AMD-761 Datasheet, PDF (110/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
DDR PDL Calibration Control
Dev0:F1:0x40
31
30
29
28
27
26
25
24
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
23
22
21
20
19
18
17
16
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
15
14
13
12
11
10
9
8
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
7
6
5
4
Bit SW_Recal Use_Act_Dly Auto_Cal_En Act_Dly_Inh
Reset
X
X
X
X
R/W
R/W
W
R/W
R/W
3
2
Reserved
0
0
R
1
0
Auto_Cal_Period
X
X
R/W
Register Description
This register allows BIOS control of the calibration circuit for the AMD-761™ system controller’s 18 programmable delay
lines.
Note that this register is not initialized at reset time but must be initialized by BIOS for proper operation. This action
should be done prior to attempting DRAM access.
98
AMD-761™ System Controller Programmer’s Interface
Chapter 2