AMD-761 Datasheet, PDF (148/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions (Continued)
AGP/PCI Interrupt and Bridge Control (Dev1:0x3C)
Bit Name
Function
20 Reserved
Reserved
19 VGA_En
VGA Enable
Affects the response by the bridge to compatible VGA addresses. When it is set, the bridge
decodes and forwards the following accesses on the primary interface to the secondary
interface.
Memory accesses in the range:
0xA0000 to 0xBFFFF
18 ISA_En
I/O address where AD[9:0] are in the ranges:
0x3B0 to 0x3BB and 0x3C0 to 0x3DF
(inclusive of ISA address aliases — AD[15:10] are not decoded)
ISA Enable
Modifies the response by the bridge to ISA I/O addresses. This modification applies only to
I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first
64 Kbytes of PCI I/O address space (0000 0000h to 0000 FFFFh). When set, the bridge
blocks any forwarding from primary to secondary of I/O transactions addressing the last
768 bytes in each 1-Kbyte block. In the opposite direction (secondary to primary), I/O
transactions are forwarded if they address the last 768 bytes in each 1-Kbyte block.
17 SERR_En
16 Par_Resp_En
15–8 Int_Pin
7–0 Int_Line
Programming Notes
0 = Forward all I/O addresses in the address range defined by the I/O Base and I/O Limit
registers.
1 = Block forwarding of ISA I/O addresses in the address range defined by the I/O Base
& I/O Limit registers that are in the first 64 Kbytes of PCI I/O address space (top 768
bytes of each 1-Kbyte block).
SERR Enable
Forwards the secondary interface SERR# assertions to the primary interface. This bit must
be set, along with the SERR enable bit (Dev 1:F0:0x04) to allow an AGP SERR# to be
propagated to the AMD-761™ system controller PCI SERR# pin. Refer to Table 7 on
page 34 for details about SERR# assertion and status.
Parity Response Enable
This bit is always 0. The AMD-761 system controller does not support parity.
Interrupt Pin
Indicates which interrupt pin the PCI-to-PCI bridge uses.
Note: This field is R/W depending on the value of the IntPinCntl bit (Bit 0 of Dev
1:0x40). Refer to “Dev1:0x40” on page 137 for details. The ability to write this
field is supported to allow BIOS to program to the required value.
The AMD-761 system controller hardware does not use this field internally in any way.
Interrupt Line
Communicates interrupt line routing information. This field is a simple R/W field to allow
BIOS software to program to the required value.
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AMD-761™ System Controller Programmer’s Interface
Chapter 2