AMD-761 Datasheet, PDF (189/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Chapter 3
Periodic auto-calibration mode re-computes the Cal_Dly values
and transfers this value into the PDLs. All nine (or 18)
calibration mechanisms are enabled/disabled together for auto-
calibration. This mode is useful in adjusting the delay values
during operation. In effect, auto-calibration can adjust for
voltage and temperature (VT) drifts during operation. Note
that the AMD-761 system controller also allows re-calibration
to occur completely under software control when this (auto-
calibration) mode is disabled.
The auto-calibration period is configurable, and the possible
periods are 10000, 1000000, 10000000 clock cycles (at 100 MHz,
these periods are equal to 100 µs, 10 ms, and 100 ms, while at
133 MHz it is somewhat faster). The setting of the auto-
calibration period should be based on the actual
characteristics of the system.
Software can control when calibration is done (except for the
first computation at reset or an exit from self-refresh). It can
either configure the AMD-761 system controller for auto-
calibration (via the Auto_Cal_En bit), or it can initiate a single
recomputation (via the SW_ReCal bit). If software initiates a
single recomputation (via the SW_Recal bit), it should also poll
for this computation to be done.
Because auto-calibration registers are not initialized at reset, it
is the responsibility of the BIOS to initialize the SW_Cal_Dly.
The SW_Cal_Dly value that BIOS provides is based on a value
provided after AMD-761 silicon characterization. The hardware
computes the Cal_Dly value that is applied to the PDL based
on the SW_Cal_Dly programmed. The SW_Cal_Dly bits are
used by AMD-761 system controller to update the delay times
in both auto-calibration mode as well as software-initiated
calibrations. For example, if the delay required is 1.7 ns and
the system clock frequency is 133 MHz, the following is the
derivation of the SW_Cal_Dly value:
„ The half-period of system clock = 3.75 ns.
„ 1.7 ns = 45.33% of the half-period.
„ The SW_Cal_Dly value is 0.4533 x 256 = 116 (rounded to
nearest integer) = 0x74.
The AMD-761 system controller allows software to optionally
write to the Act_Dly bits that control each PDL. The value
written to the Act_Dly bits is the number of buffer delays
DDR SDRAM Interface
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