AMD-761 Datasheet, PDF (181/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
3.7 ECC and Memory Scrubbing
The AMD-761 system controller DDR SDRAM controller
supports error correcting code (ECC) and memory scrubbing.
The error correction capability allows the correction of single-
bit errors and the detection of multiple-bit errors in any
memory quadword. Data is only checked by the memory
controller during a read access. A data error may be due to a
faulted bit in the DDR device itself, or a faulted bit that
occurred during data transmissions from the DDR devices to
the AMD-761 system controller memory controller. To support
the ECC function, DIMMs must support additional storage for
the ECC check bits. When ECC is enabled, the system must
have all DDR DIMMs that are 72 bits wide (also called ECC
DDR DIMMs). The AMD-761 system controller DDR SDRAM
controller provides five ECC modes. All ECC modes work
correctly with either unbuffered or registered DDR DIMMs.
The five modes supported are:
„ ECC Disabled
„ High-Performance EC Mode (EC_HiPerf mode)—Error
Checking only, no correction, except to the AMD Athlon™
processor
„ High-Performance ECC Mode (ECC_HiPerf mode)—Error
Checking and Correction
„ ECC with Scrubbing (ECC_Scrub mode)—Error Checking
and Correction with Scrubbing
„ Diagnostic ECC mode (ECC_Diag)
Each mode is discussed below.
The ECC check bits that are stored in the additional DDR
devices on the DIMM are generated by the memory controller
(based on a Hamming code algorithm) and written into the
DIMMs check bit storage during a memory write operation
when any ECC function is enabled. A single byte of check bits
represents the associated quadword of data that is written into
memory.
When any ECC mode is enabled and a read access is
performed, the memory controller internally generates check
bits based on the data value read (for each quadword of data
read) and compares it with the check bits read along with the
Chapter 3
DDR SDRAM Interface
169