AMD-761 Datasheet, PDF (198/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
4.1
Table 31. AMD-761™ System Controller Power Management Features for
ACPI Support
AMD-761 system controller Power Management Feature
ACPI State
C1 C2 S1 S3
Disconnect processor when Halt special cycle is detected on
AMD Athlon™ system bus.
X
„ Enabled by BIU Status/Control (Dev 0:F0:0x60, bit 18)
Disconnect processor when Stop Grant special cycle is detected on
AMD Athlon™ processor system bus.
„ Enabled by BIU Status/Control (Dev 0:F0:0x60, bit 17 for CPU 0)
XXX
Memory controller forces DRAM to self-refresh mode
„ Enabled by BIU Status/Control (Dev 0:F0:0x60) and Mode/Status
Register (Dev 0:F0:0x70, bit 18)
XXX
DCSTOP# assertion by Southbridge causes AMD-761 system control-
ler to gate off clock trees and DRAM clocks for lower power
„ Enabled when the Stp_Grant_Discon_En bit is set in the BIU
Status/Control Register (Dev 0:F0:0x60, bit 17).
XX
RESET# assertion in S3 state causes AMD-761 system controller to
gate off I/O rings so power can be removed from AGP, PCI, and pro-
cessor interfaces while VDD_CORE and DDR interface remains pow-
ered.
X
„ Enabled when the Stp_Grant_Discon_En bit is set in the BIU
Status/Control Register (Dev 0:F0:0x60, bit 17).
Each of the various power management features may be
optionally enabled with specific configuration bits in the
AMD-761 system controller’s host bridge configuration space as
described in the following sections.
C1 Halt State Requirements
The processor enters the C1 Halt state after executing a Halt
instruction and generating a Halt special cycle on the
AMD Athlon™ system bus. The AMD-761 system controller
supports two options for the Halt state:
1. Forward the Halt special cycle to the PCI bus but otherwise
continue normal operation (no power savings).
2. Disconnect the processor and then forward the Halt special
cycle to the PCI bus (processor enters very low-power state).
186
Power Management
Chapter 4