AMD-761 Datasheet, PDF (188/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
data byte (for x8 and x16 devices) or data nibble (for x4
devices) on a read cycle. The time value of the amount of delay
to be applied to each DQS is fixed and is only dependent on the
frequency of the system clock. Therefore, the DQS delay
required is known a priori and is listed in Table 30. What is not
known is how many internal buffer delays equal this required
time value over PVT, which is the purpose of the PDL
calibration mechanism.
Table 30. Default DQS Delay versus System Clock Frequency
System Clock
Frequency
100 MHz
133 MHz
DQS Delay
(ns)
2.0500 ns
1.5625 ns
DQS Delay (% of CCLK2X Period)
41.0%
41.7%
Because the propagation delay of an individual buffer internal
to the AMD-761 system controller is a function of PVT, a
mechanism is required to compensate for these three variables.
As previously mentioned, the delay value is known, but the
number of buffers that provides this delay value is not known
for a given PVT point. The calibration mechanism provides this
piece of information. The mechanism used is a simple
measurement of how many buffer delays are required to equal
the system clock period. Because the system clock is generated
by a PLL in the AMD-761 system controller, and it is already
compensated for PVT, the system clock period is independent
of PVT. Therefore, the clock period can be assumed to be a
constant and can be used to correlate the PDL values (Cal_Dly
and Act_Dly) to units of time.
Each calibration mechanism inside the AMD-761 system
controller measures the 2X SYSCLK period in buffer delays.
This measurement can take a few hundred clock cycles,
therefore it is done off-line. The calibration mechanism
computes a Cal_Dly value that is then transferred into the PDL
control register (Act_Dly) at a time when the DQS pins are not
active as inputs.
The calibration is automatically performed once after reset
and once after self-refresh exit, and the resultant value is
transferred to each PDL. Re-calibration can be initiated via
software. The AMD-761 system controller also has a mode that
enables periodic auto calibration.
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DDR SDRAM Interface
Chapter 3