AMD-761 Datasheet, PDF (170/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
CAS Latency
CAS latency values can occupy multiple bytes in the SPD. CAS
latency is the only item governing DIMM setup that has
multiple values. Table 24 shows CAS latency settings.
Table 24. CAS Latency Settings
Symbol
Name
SPD Byte Typical Value
Description
Max bus speed for CL=2.5 with AMD-761™
system controller.
0
DIMM does not support CL=2.5.
75h equal 7.5 ns. This DIMM can be used @
9
75h
CL = 2.5 when bus speed is less than or equal to
133 MHz.
t_CL
CAS Latency
0x0x0x54[3:2]
A0h equals 10 ns. This DIMM can be used @
A0h
CL = 2.5 when bus speed is less than or equal to
100 MHz.
Max bus speed for CL=2 with AMD-761™
system controller.
0
DIMM does not support CL=2.
75h equal 7.5 ns. This DIMM can be used @
23
75h
CL = 2 when bus speed is less than or equal to
133 MHz.
A0h equals 10 ns. This DIMM can be used @
A0h
CL = 2 when bus speed is less than or equal to
100 MHz.
Notes:
1. Other values in byte 9 represent other maximum bus speeds for CL=2.5. Should another speed occur, CL=2.5 cannot be used
beyond its max for this DIMM—that is, byte 9 = 80 means a maximum bus speed of 120 MHz. CL=2.5 can be used for a maximum
bus speed of 100 MHz, but not for 133 MHz.
2. Other values in byte 23 represent other maximum bus speeds for CL=2. Should another speed occur, CL=2 cannot be used beyond
its max for this DIMM—that is, byte 23 = 80 means a maximum bus speed of 120 MHz. CL=2 can be used for a maximum bus
speed of 100 MHz, but not for 133 MHz.
The two entries for supported CAS latency(CL) represent
different performance potential. The smaller value for CL (2)
would represent best performance. BIOS can choose from any
legal CL that exists in the SPD for the DIMM. The AMD-761
system controller supports CL values of 2, 2.5, and 3.
Other timing values in the SPD reflect minimum timings
required, based on the corresponding memory bus clock speed.
BIOS must program the memory controller configuration with
the correct timing values as specified by the DDR device.
158
DDR SDRAM Interface
Chapter 3