AMD-761 Datasheet, PDF (209/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Delayed Transactions
and Target Latency
Disabled
when the read target latency timer expires, thus allowing
the PCI target and memory controller logic to
independently complete the read so that the next time the
original master retries the read, the data is ready to return
immediately (assumes the PCI_WR_Post_Rty bit is not set
in the PCI Arbitration Register (Dev 0:F0:0x84, bit 14).
There are two reasons delayed transactions may be enabled:
1. For systems that must meet the target latency requirement,
delayed transactions are better because the memory read
cycle is queued in the AMD-761 system controller memory
controller after the PCI master is disconnected and while it
is re-arbitrating for the PCI bus. This action provides a
higher likelihood that when the master retries the
transaction, the read data is immediately available.
2. Delayed transactions free up the PCI bus during the time
that the memory subsystem is retrieving the read data, for
peer-to-peer PCI traffic between other PCI masters and
agents. Unfortunately, this type of traffic is rare in most
systems.
It should be noted that the AMD-761 system controller
supports only a single-level delayed transaction queue, thus the
performance benefit may be minimal and may actually be
worse with delayed transactions enabled under some
conditions.
The following sections provide examples of PCI read
transactions with delayed transactions enabled and disabled.
Note that in both examples the read target latency feature
enable is set the same as the delayed transaction feature
enable.
This example assumes that a memory read transaction is
initiated by a PCI master and that the AMD-761™ system
controller is unable to return data within the specified 32 PCI
clock latency.
1. The AMD-761 system controller initiates a memory read to
the memory controller and simultaneously issues a probe to
the processor. The memory subsystem is unable to return
the data within 32 PCI clocks, so it continues to hold the bus
(DEVSEL# active, STOP#, and TRDY# inactive).
Chapter 5
PCI Bus Interface
197