AMD-761 Datasheet, PDF (229/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Registers
-----
Bits
0x0x0x54h
Description
SDRAM Timing
31
SPBWaitState
AddrTiming_A
30
SPD # 21
AddrTiming_B
29
SPD # 21
28
RD_Wait_State
Reg_DIMM_En
27
SPD # 21
26
t_WTR = Write Data In to Read
Command Delay
25:24
23
22:19
t_WR = Write Recovery Time
t_RRD = Active Bank A to Active
Bank Command Delay
SPD # 28
Reserved
Idle cycle to wait before
18:16 ^{pre-charging the idle bank}
Include bit 24 above
15:14
Page Hit request before a
nonPage hit
13:12 Reserved
t_RC = Bank Cycle Time
11:9
t_RAS + t_RP
or SPD# 41(new, not yet
implemented)
8:7
t_RP = Precharge Time
SPD # 27
Initialized/
Required
Value
Actual
Value
Key fcn( )
Notes
xb
xb
xb
1b
xb
1b
10b
xb
000_0b
001b
10b
00b
xxxb
xxb
0 @ 100-MHz FSB
B FSB
1 @ 133-MHz FSB
0 @ Unbuffered DIMM
B SPD
1 @ Registered DIMM
0 @ Unbuffered
B SPD _{1 @ Registered}
B
Must = 1
0 @ Unbuffered DIMM
B SPD
1 @ Registered DIMM
0 = 1 Clock
B
1 = 2 Clocks
00b=1 Clock, 01b=Reserved
B
10b=2 Clocks, 11b=3 Clocks
0 = 2 Clocks
B SPD
1 = 3 Clocks
r
000 = 0 cyc, 001 = 8 cyc (safe)
010 = 12 cyc, 011 = 16 cyc
B
100 = 24 cyc, 101 = 32 cyc
110 = 48 cyc, 111 = Disable
B
00 = 1 cyc, 01 = 4 cyc
10 = 8 cyc (safe), 11 = 16 cyc
r
000 = 3 cyc, 001 = 4 cyc
FSB
B and ^{010 = 5 cyc, 011 = 6 cyc}
100 = 7 cyc, 101 = 8 cyc (safe)
SPD
110 = 9 cyc, 111 = 10 cyc
FSB 00 = 3 cyc (safe), 01 = 2 cyc
B _{SPD 10 = 1 cyc, 11 = 4 cyc}
KEY:
B= Mandatory BIOS function
A= AGP setup by BIOS
c = Calculated/set by AMD-761™ internal logic
P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS
r = Hardcoded and reserved
u = PCI operational user interface E = Elective BIOS function
Chapter 7
Recommended BIOS Settings
217