AMD-761 Datasheet, PDF (117/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31–30 Reserved
29–27 PSlewMDAT
26–24 NSlewMDAT
23–20 Reserved
19–18 PDrvMDAT
DDR DQS/MDAT Pad Configuration (Dev0:F1:0x8C)
Function
Reserved
MDAT Rising Edge Slew Rate
These bits control the rising edge slew rate of the MDAT[63:0] and DM[8:0] pins.
000 = Slew rate 0 (slowest)
001 = Slew rate 1
010 = Slew rate 2
011 = Slew rate 3
100 = Slew rate 4
101 = Slew rate 5
110 = Slew rate 6
111 = Slew rate 7 (fastest)
Note that the DM[8:0] pins are controlled by the PSlewDQS field when any chip select is
configured for x4 DIMMs in the DRAM Mode/Status register (Dev 0:F0:0x58).
MDAT Falling Edge Slew Rate
These bits control the falling edge slew rate of the MDAT[63:0] and DM[8:0] pins.
000 = Slew rate 0 (slowest)
001 = Slew rate 1
010 = Slew rate 2
011 = Slew rate 3
100 = Slew rate 4
101 = Slew rate 5
110 = Slew rate 6
111 = Slew rate 7 (fastest)
Note that the DM[8:0] pins are controlled by the NSlewDQS field when any chip select is
configured for x4 DIMMs in the DRAM Mode/Status register (Dev 0:F0:0x58).
Reserved
MDAT P Transistor Drive Strength
These bits control the P transistor drive strength of the MDAT[63:0] and DM[8:0] pins.
00 = Drive strength 0 (weakest)
01 = Drive strength 1
10 = Drive strength 2
11 = Drive strength 3 (strongest)
Note that the DM[8:0] pins are controlled by the PDrvDQS field when any chip select is
configured for x4 DIMMs in the DRAM Mode/Status register (Dev 0:F0:0x58).
Chapter 2
AMD-761™ System Controller Programmer’s Interface
105