AMD-761 Datasheet, PDF (112/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions (Continued)
DDR PDL Calibration Control (Dev0:F1:0x40)
Bit Name
Function
4 Act_Dly_Inh
Actual Delay Update Inhibit
This bit configures the hardware to either update the actual PDLs (Act_Dly values) with
new Cal_Delay values or not. The setting of this bit affects both auto-calibration and
SWCalibration but not the Use_Act_Dly method. After an exit from power-on reset or self-
refresh, the setting of this bit determines whether the Act_Dly value is updated or not.
0 = Update all the PDLs with new Cal_Dly values in hardware after recomputation is
done (default).
1 = Do not update the Actual PDL delay values after recomputation of Cal_Dly is done.
Note: The internal logic tests this bit just prior to updating the Act_Dly, so the other
bits in this register should be taken into consideration when writing to this bit.
3–2 Reserved
Reserved
1–0 Auto_Cal_Period Auto-Calibration Period
This bit field defines how often auto-calibration is performed.
00 = 10000 system clocks
01 = 1000000 system clocks
10 = 10000000 system clocks
11 = Reserved
BIOS should configure this field before setting the Auto_Cal_En bit, and while Auto_Cal_En
is set, do not write to this field.
Programming Notes
Note that this register is not initialized at reset time, but must be initialized by BIOS for proper operation. This action
should be done prior to attempting DRAM access.
See Table 13 for PDL calibration modes.
Table 13. PDL Calibration Modes
Auto_Cal_En
0
0
0
0
Use_Act_Delay
0
0
1
1
1
X
SW_ReCal
0
1
0
1
X
Resultant Operation
No action.
SW_Cal_Dly values are applied.
Act_Dly values are applied.
Illegal combination (do not use).
SW_Cal_Dly values are applied according to the
Auto_Cal_Period setting. Do not set the Act_Dly or
SW_Recal bits.
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AMD-761™ System Controller Programmer’s Interface
Chapter 2