XR72L52 Datasheet, PDF (93/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
These two bits reflect the states of the SSM Multi-frame phase indicators, within the most recently received E3
frame. Stated another ways, these two bit-fields reflect Bits 2 and 1 within the MA byte, in the most recently re-
ceived E3 frame.
NOTE: These two bit-fields are only valid if the Receive Section of the Channel has been configured to support the October
1998 Revision of the ITU-T G.832 Framing format for E3.
Bits 3-0 - RxSSM[3:0] - Received Synchronization Status Message
These four Read-Only bits reflect the content of the SSM, which is currently being received via the inbound E3
data stream.
NOTE: These four bit-fields are only valid if the Receive Section of the Channel has been configured to support the October
1998 Revision of the ITU-T G.832 Framing format for E3.
2.3.4 Receive E3 Framer Configuration Registers (ITU-T G.751)
NOTE: Device powers-up in E3 G.751 mode by default.
2.3.4.1 Receive E3 Configuration & Status Register 1 (E3, ITU-T G.751)
RXE3 CONFIGURATION & STATUS REGISTER 1 (ADDRESS = 0X10)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
RxFERF
Algo
Reserved
RxBIP4
RO
RO
RO
R/W
RO
RO
RO
R/W
0
0
0
0
0
0
1
0
Bit 4 - RxFERF Algo(rithm) Select
This Read/Write bit-field permits the user to select the Received FERF Declaration Algorithm.
Setting this bit-field to "0", configures the Receive Section of the Channel to declare a FERF (Far-End-Receive
Failure), after three (3) consecutive E3 frames, with the A-Bit set to "1", have been received. Further, the Re-
ceive Section of the Channel will clear FERF, after three (3) consecutive E3 frames, with the A-Bit set to "0",
have been received.
Setting this bit-field to "1", configures the Receive Section of the Channel to declare a FERF, after five (5) con-
secutive E3 frames, with the A-Bit set to "1", have been received. Further, the Receive Section of the Channel
will clear FERF after five (5) consecutive E3 frames, with the A-Bit set to "0", have been received.
Bit 0 - RxBIP4 Enable
This Read/Write bit-field permits the user to configure the Receive Section of the Channel to verify (or not veri-
fy) the BIP-4 value within each incoming E3 frame.
Setting this bit-field to "0", configures the Receive Section of the Channel to NOT verify the BIP-4 value within
each incoming E3 frame.
Setting this bit-field to "1", configures the Receive Section of the Channel to verify the BIP-4 value within each
incoming E3 frame.
2.3.4.2 Receive E3 Configuration & Status Register 2 (E3, ITU-T G.751)
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxLOF
Algo
RxLOF
RxOOF
RxLOS
RxAIS
Not Used
RxFERF
R/W
RO
RO
RO
RO
RO
RO
RO
0
1
1
1
0
0
1
0
77