XR72L52 Datasheet, PDF (13/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55)........................................................ 310
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) .............................................................................. 310
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) ................................................................... 311
5.3.3 The Receive HDLC Controller Block .................................................................................................... 311
Figure 130. LAPD Message Frame Format.................................................................................................................. 312
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18 .............................................................................. 312
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................ 313
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................ 313
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................ 314
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................ 314
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................ 315
TABLE 59: THE RELATIONSHIP BETWEEN THE CONTENTS OF RXLAPDTYPE[1:0] BIT-FIELDS AND THE PMDL MESSAGE TYPE/SIZE
315
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18 .............................................................................. 315
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) ................................................................................ 316
Figure 131. Flow Chart depicting the Functionality of the LAPD Receiver ................................................................... 317
5.3.4 The Receive Overhead Data Output Interface ..................................................................................... 317
Figure 132. The Receive Overhead Output Interface block ......................................................................................... 318
Figure 133. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface (Method 1) .. 319
TABLE 60: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
(FOR METHOD 1)............................................................................................................................................. 319
TABLE 61: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXOHFRAME WAS LAST
SAMPLED "HIGH”) TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN...................... 320
Figure 134. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method 1). ...... 320
TABLE 62: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
(METHOD 2) .................................................................................................................................................... 321
Figure 135. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface (Method 2) .. 322
TABLE 63: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES (SINCE RXOHFRAME WAS LAST SAMPLED
"HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN .................................... 322
Figure 136. Illustration of the signals that are output via the Receive Overhead Data Output Interface block (for Method 2).
323
5.3.5 The Receive Payload Data Output Interface........................................................................................ 323
Figure 137. The Receive Payload Data Output Interface block.................................................................................... 323
TABLE 64: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK
326
Figure 138. The Terminal Equipment being interfaced to the Receive Payload Data Input Interface Block (Serial Mode
Operation)...................................................................................................................................................... 327
Figure 139. An Illustration of the behavior of the signals between the Receive Payload Data Output Interface block of the
XRT72L52 and the Terminal Equipment........................................................................................................ 328
Figure 140. The XRT72L52 DS3/E3 Framer IC being interfaced to the Receive Section of the Terminal Equipment (Nibble-
Parallel Mode Operation)............................................................................................................................... 329
Figure 141. Illustration of the signals that are output via the Receive Payload Data Output Interface block (for Nibble-Parallel
Mode Operation)............................................................................................................................................ 330
5.3.6 Receive Section Interrupt Processing .................................................................................................. 330
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ....................................................................... 331
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ................................................................... 331
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................... 332
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ........................................................ 332
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ................................................................... 333
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................... 333
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) .......................................................... 333
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ................................................................... 334
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ........................................................ 334
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ................................................................... 335
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................... 335
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ........................................................ 336
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ................................................................. 336
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................... 337
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) ................................................................... 337
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................... 338
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