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XR72L52 Datasheet, PDF (278/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
TABLE 44: A LISTING OF THE OVERHEAD BITS WITHIN THE E3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN THE
XRT72L52 IC
OVERHEAD BIT
FAS Signal - Bit 6
FAS Signal - Bit 5
INTERNALLY GENERATED
Yes
Yes
ACCESSIBLE VIA THE TRANSMIT OVERHEAD
DATA INPUT INTERFACE
No
No
BUFFER/REGISTER
ACCESSIBLE
Yes
Yes
FAS Signal - Bit 4
Yes
FAS Signal - Bit 3
Yes
No
Yes
No
Yes
FAS Signal - Bit 2
Yes
FAS Signal - Bit 1
Yes
No
Yes
No
Yes
FAS Signal - Bit 0
Yes
No
Yes
A Bit
Yes
N Bit
Yes
Yes
Yes
Yes
Yes
NOTES:
1. The XRT72L52 contains mask register bits that permit the user to alter the state of the internally generated value
for these bits.
2. The Transmit LAPD Controller/Buffer can be configured to be the source of the N bits, within the outbound E3 data
stream.
The Transmit Overhead Data Input Interface permits the user to insert overhead data into the outbound E3
frames via the following two different methods.
• Method 1 - Using the TxOHClk clock signal
• Method 2 - Using the TxInClk and the TxOHEnable signals.
Each of these methods are described below.
5.2.2.1 Method 1 - Using the TxOHClk Clock Signal
The Transmit Overhead Data Input Interface consists of the five signals. Of these five (5) signals, the following
four (4) signals are to be used when implementing Method 1.
• TxOH
• TxOHClk
• TxOHFrame
• TxOHIns
Each of these signals are listed and described below.
Table 45.
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