XR72L52 Datasheet, PDF (160/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
The XRT72L52 operating in this mode functions as the source of the 11.184MHz (e.g., the 44.736MHz clock
signal divided by 4) clock signal that is used as the Terminal Equipment Interface clock by both the XRT72L52
and the Terminal Equipment.
The Terminal Equipment outputs the payload data of the outbound DS3 data stream via its DS3_Data_Out[3:0]
pins on the rising edge of the 11.184MHz clock signal at the DS3_Nib_Clock_In input pin.
The XRT72L52 latches the outbound DS3 data stream from the Terminal Equipment on the rising edge of the
TxNibClk output clock signal. The XRT72L52 indicates that it is processing the last nibble within a given DS3
frame by pulsing its TxNibFrame output pin "High" for one TxNibClk clock period. When the Terminal Equip-
ment detects a pulse at its Tx_Start_of_Frame input pin, it is expected to transmit the first nibble of the very
next outbound DS3 frame to the XRT72L52 via the DS3_Data_Out[3:0] or TxNib[3:0] pins.
Finally, for the Nibble-Parallel Mode operation, the XRT72L52 continuously pulls the TxOHInd output pin
"Low".
The behavior of the signals between the XRT72L52 and the Terminal Equipment for DS3 Mode 4 Operation is
illustrated in Figure 39.
FIGURE 39. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L52 AND THE TERMINAL
EQUIPMENT (MODE 4 OPERATION)
Terminal Equipment Signals
RxOutClk
DS3_Nib_Clock_In
DS3_Data_Out[3:0]
Tx_Start_of_Frame
Nibble [1175]
Nibble [0]
XRT72L5x Transmit Payload Data I/F Signals
RxOutClk
TxNibClk
TxNib[3:0]
TxNibFrame
Nibble [1175]
Nibble [0]
DS3 Frame Number N
Note: TxNibFrame pulses high to denote
DS3 Frame Boundary.
Sampling Edge of XRT72L5x Device
DS3 Frame Number N + 1
How to configure the XRT72L52 into Mode 4
1. Set the NibIntf input pin "High".
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