XR72L52 Datasheet, PDF (322/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
• Generate a Change in FERF Condition interrupt to the Microprocessor. Hence, the Receive E3 Framer
block will assert Bit 3 (FERF Interrupt Status) within the Rx E3 Framer Interrupt Status register - 2, as
depicted below.
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
FERF
Interrupt
Status
RUR
1
BIT 2
BIP-4
Error
Interrupt
Status
RUR
0
BIT 1
Framing
Error
Interrupt
Status
RUR
0
BIT 0
Not Used
RUR
0
• Set the RxFERF bit-field, within the Rx E3 Configuration/Status Register to “1”, as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
RxLOF
Algo
R/W
0
BIT 6
RxLOF
RO
1
BIT 5
RxOOF
RO
1
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
0
BIT 2
BIT 1
Not Used
RO
RO
0
0
BIT 0
RxFERF
RO
1
Clearing the FERF Condition
The Receive E3 Framer block will clear the FERF condition once it has received a User-Selectable number of
E3 frames with the A bit-field being set to “0” (e.g., no FERF condition). This User-Selectable number of E3
frames is either 3 or 5 depending upon the value that has been written into Bit 4 (RxFERF Algo) of the Rx E3
Configuration/Status Register, as discussed above.
Whenever the Receive E3 Framer clears the FERF status, then it will do the following:
1. Generate a Change in the FERF Status Interrupt to the Microprocessor.
2. Clear the Bit 0 (RxFERF) within the Rx E3 Configuration & Status register, as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
RxLOF
Algo
R/W
0
BIT 6
RxLOF
RO
1
BIT 5
RxOOF
RO
1
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
0
BIT 2
BIT 1
Not Used
RO
RO
1
1
BIT 0
RxFERF
RO
0
5.3.2.10 Error Checking of the Incoming E3 Frames
The Receive E3 Framer block can be configured to perform error-checking on the incoming E3 frame data that
it receives from the Remote Terminal Equipment. If configured accordingly, the Receive E3 Framer block will
perform this error-checking by computing the BIP-4 value of an incoming E3 frame. Once the Receive E3
Framer block has obtained this value, it will compare this value with that of the BIP-4 value that it receives,
within the very next E3 frame. If the locally computed BIP-4 value matches the EM byte of the corresponding
E3 frame, then the Receive E3 Framer block will conclude that this particular frame has been properly re-
ceived. The Receive E3 Framer block will then inform the Remote Terminal Equipment of this fact by having
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