XR72L52 Datasheet, PDF (242/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FIGURE 83. THE XRT72L52 DS3/E3 FRAMER IC BEING INTERFACED TO THE RECEIVE SECTION OF THE TERMINAL
EQUIPMENT (NIBBLE-PARALLEL MODE OPERATION)
Rx_DS3_Clock_In
DS3_Data_In[3:0]
Rx_Start_of_Frame
11.184MHz
Clock Signal
RxClk
RxNib[3:0]
RxLineClk
RxFrame
44.736MHz
Clock Source
Terminal Equipment
Receive Payload Section
DS3 Framer
Required Operation of the Terminal Equipment
The XRT72L52 will update the data on the RxNib[3:0] line, upon the falling edge of RxClk. Hence, the Terminal
Equipment should sample the data on the RxNib[3:0] output pins (or the DS3_Data_In[3:0] input pins at the
Terminal Equipment) upon the rising edge of RxClk. As the Terminal Equipment samples RxSer with each ris-
ing edge of RxClk it should also be sampling the RxFrame signal.
The Need for Sampling RxFrame
The XRT72L52 will pulse the RxFrame output pin "High" coincident with it driving the very first nibble of a given
DS3 frame, onto the RxNib[3:0] output pins. If knowledge of the DS3 Frame Boundaries is important for the
operation of the Terminal Equipment, then this is a very important signal for it to sample.
NOTE: For DS3/Nibble-Parallel Mode Operation, none of the Overhead bits will be output via the RxNib[3:0] output pins.
Hence, the RxOH_Ind output pin will be in-active in this mode.
The Behavior of the Signals between the Receive Payload Data Output Interface block and the Terminal
Equipment
The behavior of the signals between the XRT72L52 and the Terminal Equipment for DS3 Nibble-Mode opera-
tion is illustrated in Figure 84.
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