XR72L52 Datasheet, PDF (35/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
PIN DESCRIPTION
PIN #
150
151
152
153
154
PIN NAME
DMO[0]
ExtLOS[0]
RLOL[0]
GND
NC
TYPE
DESCRIPTION
I Drive Monitor Output Input (from the XRT73L0x DS3/E3 Line Interface Unit
IC):
This input pin is intended to be connected to the DMO output pin of the
XRT73L0x DS3/E3 Line Interface Unit IC. To determine the state of this input
pin, read Bit 2 (DMO) within the Line Interface Scan Register (Address = 0x81).
If this input signal is "High", the drive monitor circuitry within the XRT73L0x DS3/
E3 Line Interface Unit IC has not detected any bipolar signals at the MTIP and
MRING inputs within the last 128 32 bit-periods. If this input signal is "Low", then
bipolar signals are being detected at the MTIP and MRING input pins of the
XRT73L0x.
If the XRT73L0x DS3/E3 Line Interface Unit IC is not used, this input pin may be
used for other purposes.
I Receive LOS (Loss of Signal) Indicator Input (from XRT73L0x LIU IC):
This input pin is intended to be connected to the RLOS output pin of the
XRT73L0x Line Interface Unit IC. To monitor the state of this pin, read the state
of Bit 0 (RLOS) within the Line Interface Scan Register (Address = 0x81).
If this input pin is "Low", then the XRT73L0x is currently NOT declaring an LOS
condition. If this input pin is "High", then the XRT73L0x is currently declaring an
LOS (Loss of Signal) condition.
For more information on the operation of the XRT73L0x DS3/E3 Line Receiver
IC, please consult the XRT73L0x DS3/STS-1/E3 Line Interface Unit IC data
sheet.
Asserting the RLOS input pin causes the XRT72L52 DS3/E3 Framer to declare
an LOS condition. Therefore, this input pin should not be used as a general pur-
pose input pin.
I Receive Loss of Lock Indicator - from the XRT73L0x DS3/E3 Line Interface
Unit IC:
This input pin is intended to be connected to the RLOL output pin of the
XRT73L0x Line Interface Unit IC. To monitor the state of this pin, read the state
of Bit 1 (RLOL) within the Line Interface Scan Register (Address = 0x81).
If this input pin is "Low", then the clock recovery phase-locked-loop circuitry
within the XRT73L0x is properly locked onto the incoming DS3 E3 data-stream
and is properly recovering clock and data from this DS3/E3 data-stream. If this
input pin is "High", then the phase-locked-loop circuitry within the XRT73L0x has
lost lock with the incoming DS3 or E3 data-stream and is not properly recovering
clock and data.
For more information on the operation of the XRT73L0x DS3/E3 Line Interface
Unit IC, please consult the XRT73L0x DS3/E3 Line Interface Unit data sheet.
If the XRT73L0x DS3/E3 Line Interface Unit IC is not used, this input pin may be
used for other purposes.
**** Ground
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