XR72L52 Datasheet, PDF (197/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
TABLE 29: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR) WITHIN THE UNI I/O
CONTROL REGISTER AND THE TRANSMIT DS3 FRAMER LINE INTERFACE OUTPUT MODE
BIT 3
0
1
TRANSMIT DS3 FRAMER LIU INTERFACE OUTPUT MODE
Bipolar Mode: AMI or B3ZS Line Codes are Transmitted and Received
Unipolar (Single Rail) Mode of transmission and reception of DS3 data is selected.
NOTES:
1. The default condition is the Bipolar Mode.
2. This selection also effects the operation of the Receive DS3 LIU Interface block
4.2.5.1.1 The Bipolar Mode Line Codes
If framer is to be operated in the Bipolar Mode, then the DS3 data-stream can be transmitted via the AMI (Al-
ternate Mark Inversion) or the B3ZS Line Codes. The definition of AMI and B3ZS line codes follow.
4.2.5.1.1.1 The AMI Line Code
AMI or Alternate Mark Inversion, means that consecutive one's pulses (or marks) will be of opposite polarity
with respect to each other. The line code involves the use of three different amplitude levels: +1, 0, and -1. +1
and -1 amplitude signals are used to represent one's (or mark) pulses and the "0" amplitude pulses (or the ab-
sence of a pulse) are used to represent zeros (or space) pulses. The general rule for AMI is: if a given mark
pulse is of positive polarity, then the very next mark pulse will be of negative polarity and vice versa. This alter-
nating-polarity relationship exists between two consecutive mark pulses, independent of the number of 'zeros'
that may exist between these two pulses. Figure 56 presents an illustration of the AMI Line Code as would ap-
pear at the TxPOS and TxNEG pins of the Framer, as well as the output signal on the line.
FIGURE 56. ILLUSTRATION OF AMI LINE CODE
Data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
TxPOS
TxNEG
Line Signal
NOTE: One of the main reasons that the AMI Line Code has been chosen for driving transformer-coupled media is that this
line code introduces no dc component, thereby minimizing dc distortion in the line.
4.2.5.1.1.2 The B3ZS Line Code
The Transmit DS3 Framer and the associated LIU IC combine the data and timing information (originating from
the TxLineClk signal) into the line signal that is transmitted to the far-end receiver. The far-end receiver has
the task of recovering this data and timing information from the incoming DS3 data stream. Many clock and
data recovery schemes rely on the use of Phase Locked Loop technology. Phase-Locked-Loop (PLL) technol-
ogy for clock recovery relies on transitions in the line signal, in order to maintain lock with the incoming DS3 da-
ta stream. However, PLL-based clock recovery scheme, are vulnerable to the occurrence of a long stream of
consecutive zeros (e.g., the absence of transitions). This scenario can cause the PLL to lose lock with the in-
coming DS3 data, thereby causing the clock and data recovery process of the receiver to fail. Therefore, some
approach is needed to insure that such a long string of consecutive zeros can never happen. One such tech-
nique is B3ZS encoding. B3ZS (or Bipolar 3 Zero Substitution) is a form of AMI line coding that implements the
following rule.
181