XR72L52 Datasheet, PDF (122/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
This Read/Write bit-field permits the user to define the value of the A-Bit within a given outbound E3 frame. If
the user has configured the source of the A-Bit to be the TxE3 Service Bits Register (by setting TxASource[1:0]
= 00, within the TxE3 Configuration Register, Address = 0x30), then the value written in this bit-field will specify
the value of the A-Bit within the outbound E3 Frame.
Bit 0 - N-Bit
This Read/Write bit-field permits the user to define the value of the N-Bit within a given outbound E3 frame. If
the user has configured the source of the N-Bit to be the TxE3 Service Bits Register (by setting TxNSource[1:0]
= 00, within the TxE3 Configuration Register, Address = 0x30), then the value written in this bit-field will specify
the value of the N-Bit within the outbound E3 Frame.
2.3.7.5 Transmit E3 FAS Mask Register - 0 (ITU-T G.751)
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
TxFAS_Error_Mask_Upper[4:0]
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 4 - 0, TxFAS_Error_Mask_Upper[4:0]
This Read/Write bit-field permits the user to insert errors into the upper five bits of the Framing Alignment Sig-
nal, FAS of each outbound E3 frame. The user may wish to do this for equipment testing purposes. Prior to
transmission, the Transmit E3 Framer block reads in the upper five (5) bits of the FAS value, and performs an
XOR operation with it and the contents of this register. The results of this operation are written back into the
upper five (5) bits of the FAS value, in each outbound E3 frame. Consequently, to insure errors are not injected
into the FAS of the outbound E3 frames, the contents of this register must be set to all "0’s" (the default value).
2.3.7.6 Transmit E3 FAS Error Mask Register - 1 (ITU-T G.751)
TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
TxFAS_Error_Mask_Lower[4:0]
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 4 - 0, TxFAS_Error_Mask_Lower[4:0]
This Read/Write bit-field permits the user to insert errors into the lower five bits of the Framing Alignment Sig-
nal, FAS of each outbound E3 frame. The user may wish to do this for equipment testing purposes. Prior to
transmission, the Transmit E3 Framer block reads in the lower five (5) bits of the FAS value, and performs an
XOR operation with it and the contents of this register. The results of this operation are written back into the
lower five (5) bits of the FAS value, in each outbound E3 frame. Consequently, to insure errors are not injected
into the FAS of the outbound E3 frames, the contents of this register must be set to all "0’s" (the default value).
2.3.7.7 Transmit E3 BIP-4 Error Mask Register (ITU-T G.751)
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
TxBIP-4 Mask[3:0]
RO
RO
RO
RO
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
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