XR72L52 Datasheet, PDF (354/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
• It will set Bit 3 (FERF Interrupt Status), within the Rx E3 Interrupt Status Register - 2 to “1”, as indicated
below.
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
FERF
Interrupt
Status
BIP-4
Error
Interrupt
Status
Framing
Error
Interrupt
Status
Not Used
RO
RO
RO
RO
RUR
RUR
RUR
RUR
0
0
0
0
1
0
0
0
Whenever the user’s system encounters the Change in Receive FERF Condition Interrupt, then it should do
the following.
1. It should determine the current state of the FERF condition. Recall, that this interrupt can be generated,
whenever the XRT72L52 Framer IC declares or clears the FERF defect. Hence, the user can determine
the current state of the FERF defect by reading the state of Bit 0 (RxFERF) within the Rx E3 Configuration
and Status Register - 2, as illustrated below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
RxLOF
Algo
R/W
0
BIT 6
RxLOF
RO
1
BIT 5
RxOOF
RO
1
BIT 4
RxLOS
RO
0
BIT 3
RxAIS
RO
0
BIT 2
BIT 1
Not Used
RO
RO
1
1
BIT 0
RxFERF
RO
1
5.3.6.2.7 The Detection of BIP-4 Error Interrupt
If the Detection of BIP-4 Error Interrupt is enabled, then the XRT72L52 Framer IC will generate an interrupt,
anytime the Receive E3 Framer block has detected an error in the BIP-4 Nibble, within an incoming E3 frame.
NOTE: This interrupt is only active if the XRT72L52 Framer IC has been configured to process the BIP-4 nibble within each
incoming and outbound E3 frame.
Enabling and Disabling the Detection of FEBE Event Interrupt
The user can enable or disable the Detection of BIP-4 Error’ interrupt by writing the appropriate value into Bit 2
(BIP-4 Interrupt Enable) within the Rx E3 Interrupt Enable Register - 2, as indicated below.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
R/W
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
BIT 1
BIP-4 Error
Interrupt
Enable
Framing Error
Interrupt
Enable
R/W
R/W
X
0
BIT 0
Not Used
RO
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Detection of the BIP-4 Error Interrupt
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