XR72L52 Datasheet, PDF (305/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
The user can enable or disable these Transmit Section interrupts, at the Block Level by writing the appropriate
data into Bit 1 (Tx DS3/E3 Interrupt Enable) within the Block Interrupt Enable register (Address = 0x04), as il-
lustrated below.
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7
RxDS3/E3
Interrupt
Enable
R/W
0
BIT 6
RO
0
BIT 5
BIT 4
Not Used
BIT 3
RO
RO
RO
0
0
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Enable
R/W
0
BIT 0
One-Second
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables the Transmit Section (at the Block Level) for Interrupt Generation. Con-
versely, setting this bit-field to “0” disables the Transmit Section for interrupt generation.
What does it mean for the Transmit Section Interrupts to be enabled or disabled at the Block Level?
If the Transmit Section is disabled (for interrupt generation) at the Block Level, then ALL Transmit Section inter-
rupts are disabled, independent of the interrupt enable/disable state of the source level interrupts.
If the Transmit Section is enabled (for interrupt generation) at the block level, then a given interrupt will be en-
abled if it is also enabled at the source level. Conversely, if the Transmit Section is enabled (for interrupt gen-
eration) at the Block level, then a given interrupt will still be disabled, if it is disabled at the source level.
As mentioned earlier, the Transmit Section of the XRT72L52 Framer IC contains the Completion of Transmis-
sion of LAPD Message Interrupt.
The Enabling/Disabling and Servicing of this interrupt is presented below.
5.2.6.1.1 The Completion of Transmission of the LAPD Message Interrupt
If the Transmit Section interrupts have been enabled at the Block level, then the user can enable or disable the
Completion of Transmission of a LAPD Message Interrupt, by writing the appropriate value into Bit 1 (TxLAPD
Interrupt Enable) within the Tx E3 LAPD Status & Interrupt Register (Address = 0x34), as illustrated below.
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
TXDL Start
BIT 2
TXDL Busy
R/W
RO
0
0
BIT 1
TxLAPD
Interrupt
Enable
R/W
X
BIT 0
TxLAPD
Interrupt
Status
RUR
0
Setting this bit-field to “1’ enables the Completion of Transmission of a LAPD Message Interrupt. Conversely,
setting this bit-field to “0” disables the Completion of Transmission of a LAPD Message interrupt.
5.2.6.1.2 Servicing the Completion of Transmission of a LAPD Message Interrupt
As mentioned previously, once the user commands the LAPD Transmitter to begin its transmission of a LAPD
Message, it will do the following.
1. It will compute the FCS (Frame Check Sequence) value over the contents of 0x86 through 0xDB and
append this 16 bit value to the back-end of the user-message.
2. It will parse through the contents of the Transmit LAPD Message Buffer (located at address locations 0x86
through 0xDB and the FCS bytes) and search for a string of five (5) consecutive “1’s”. If the LAPD Trans-
mitter finds a string of five consecutive “1’s” (within the content of the LAPD Message Buffer, then it will
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