XR72L52 Datasheet, PDF (273/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
FIGURE 96. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK FOR MODE 5 (NIBBLE-PARALLEL/LOCAL-TIMED/FRAME-SLAVE) OPERATION
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
34.368MHz
Clock Source
8.592MHz
4
TxInClk
TxNibClk
VCC
NibIntf
TxNib[3:0]
TxFrameRef
TxOH_Ind
Terminal Equipment
E3 Framer
Mode 5 Operation of the Terminal Equipment
In Figure 96 both the Terminal Equipment and the XRT72L52 will be driven by an external 8.592MHz clock sig-
nal. The Terminal Equipment will receive the 8.592MHz clock signal via the E3_Nib_Clock_In input pin. The
XRT72L52 will output the 8.592MHz clock signal via the TxNibClk output pin.
The Terminal Equipment will serially output the data on the E3_Data_Out[3:0] pins, upon the rising edge of the
signal at the E3_Clock_In input pin.
NOTE: The E3_Data_Out[3:0] output pins of the Terminal Equipment is electrically connected to the TxNib[3:0] input pins.
The XRT72L52 will latch the data, residing on the TxNib[3:0] input pins, on the rising edge of the TxNibClk sig-
nal.
In this case, the Terminal Equipment has the responsibility of providing the framing reference signal by pulsing
the Tx_Start_of_Frame output pin (and in turn, the TxFrameRef input pin of the XRT72L52) "High" for one bit-
period, coincident with the first bit of a new E3 frame. Once the XRT72L52 detects the rising edge of the input
at its TxFrameRef input pin, it will begin generation of a new E3 frame.
Finally, the XRT72L52 will always internally generate the Overhead bits, when it is operating in both the E3 and
Nibble-parallel modes. The XRT72L52 will pull the TxOHInd input pin "Low".
The behavior of the signals between the XRT72L52 and the Terminal Equipment for E3 Mode 5 Operation is il-
lustrated in Figure 97.
257