XR72L52 Datasheet, PDF (162/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
Nominally, the Transmit Section within the XRT72L52 generates a TxNibClk pulse for every 4 RxOutClk or Tx-
InClk periods. However, in 14 cases within a DS3 frame period, the Transmit Payload Data Input Interface al-
lows 5 TxInClk periods to occur between two consecutive TxNibClk pulses.
Interfacing the Transmit Payload Data Input Interface block of the XRT72L52 to the Terminal Equipment
for Mode 5 Operation
This is illustrated in Figure 40
FIGURE 40. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK FOR MODE 5 (NIBBLE-PARALLEL/LOCAL-TIMED/FRAME-SLAVE) OPERATION
DS3_Nib_Clock_In
DS3_Data_Out[3:0]
Tx_Start_of_Frame
44.736MHz
Clock Source
11.184MHz
4
VCC
TxInClk
TxNibClk
TxNib[3:0]
TxFrameRef
NibIntf
Terminal Equipment
DS3 Framer
Mode 5 Operation of the Terminal Equipment
In Figure 40, both the Terminal Equipment and the XRT72L52 is driven by an external 11.184MHz clock signal.
The Terminal Equipment receives the 11.184MHz clock signal via the DS3_Nib_Clock_In input pin. The
XRT72L52 outputs the 11.184MHz clock signal via the TxNibClk output pin.
The Terminal Equipment serially outputs the data on the DS3_Data_Out[3:0] pins upon the rising edge of the
signal at the DS3_Clock_In input pin. The DS3_Data_Out[3:0] output pins of the Terminal Equipment is electri-
cally connected to the TxNib[3:0] input pins.
The XRT72L52 latches the data residing on the TxNib[3:0] input pins on the rising edge of the TxNibClk signal.
In this case, the Terminal Equipment has the responsibility of providing the framing reference signal by pulsing
the Tx_Start_of_Frame output pin and in turn, the TxFrameRef input pin of the XRT72L52 "High" for one bit-pe-
riod coincident with the first nibble of a new DS3 frame. Once the XRT72L52 detects the rising edge of the in-
put at its TxFrameRef input pin, it begins generation of a new DS3 frame.
Finally, the XRT72L52 always internally generates the Overhead bits when it is operating in both the DS3 and
Nibble-parallel modes. The XRT72L52 pulls the TxOHInd input pin "Low".
The behavior of the signals between the XRT72L52 and the Terminal Equipment for DS3 Mode 5 Operation is
illustrated in Figure 41.
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