XR72L52 Datasheet, PDF (355/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
Whenever the XRT72L52 Framer IC detects this interrupt, it will do the following.
• It will assert the Interrupt Request output pin (Int), by driving it "High".
• It will set the Bit 2 (BIP-4 Interrupt Status), within the RxE3 Interrupt Status Register - 2 as indicated below.
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
FERF
Interrupt
Status
RUR
0
BIT 2
BIP-4
Error
Interrupt
Status
RUR
1
BIT 1
Framing
Error
Interrupt
Status
RUR
0
BIT 0
Not Used
RUR
0
Whenever the Terminal Equipment encounters the Detection of BIP-4 Error Interrupt, it should do the following.
• It should read the contents of the PMON Parity Error Event Count Registers (located at Addresses 0x54 and
0x55) in order to determine the number of BIP-4 Errors that have been received by the XRT72L52 Framer
IC.
5.3.6.2.8 The Detection of Framing Error Interrupt
If the Detection of Framing Error Interrupt is enabled, then the XRT72L52 Framer IC will generate an interrupt,
anytime the Receive E3 Framer block has received an E3 frame with an incorrect FAS pattern value.
Enabling and Disabling the Detection of Framing Error Interrupt
The user can enable or disable the Detection of Framing Error’ interrupt by writing the appropriate value into
Bit 1 (Framing Error Interrupt Enable) within the Rx E3 Interrupt Enable Register - 2, as indicated below.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
R/W
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
BIT 1
BIP-4 Error
Interrupt
Enable
Framing Error
Interrupt
Enable
R/W
R/W
0
X
BIT 0
Not Used
RO
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Detection of Framing Error Interrupt
Whenever the XRT72L52 Framer IC detects this interrupt, it will do the following.
• It will assert the Interrupt Request output pin (Int), by driving it "High".
• It will set the Bit 1 (Framing Error Interrupt Status), within the RxE3 Interrupt Status Register - 2 as indicated
below.
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