XR72L52 Datasheet, PDF (406/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
Setting this bit-field to "0" configures the Transmit DS3/E3 Framer block to set the FEBE and FERF bit-fields
(within the outbound E3 data stream) to the values residing within the FEBE and FERF bit-fields within the
TxE3 MA Byte Register (Address = 0x36), as illustrated below.
BIT 7
FERF
R/W
X
BIT 6
FEBE
R/W
X
BIT 5
R/W
0
BIT 4
PLDType
R/W
1
BIT 3
R/W
0
BIT 2
BIT 1
Payload Dependent
R/W
R/W
0
0
BIT 0
Timing Marker
R/W
0
6.2.4.2.2 Configuring the Transmit Trail Trace Buffer Message
The XRT72L52 Framer IC contains 16 bytes worth of Transmit Trail Trace Buffer registers and 16 bytes worth
of Receive Trail Trace Buffer registers. The role of the Receive Trail Trace Buffer registers are described in
Section 6.1.1.3.
The XRT72L52 Framer IC contains 16 Transmit Trail Trace Buffer registers (e.g., Tx TTB-0 through TxTTB-
15). The purpose of these registers are to provide a 16-byte Trail Access Point Identifier to the Remote Termi-
nal Equipment. The Remote Terminal Equipment will use this information in order to verify that it is still receiv-
ing data from its intended transmitter. The specific use of these registers follows.
For Trail Trace Buffer Message purposes, the Transmit E3 Framer block will group 16 consecutive E3 frames,
into a Trail Trace Buffer super-frame. When the Transmit E3 Framer block is generating the first E3 frame,
within a Trail Trace Buffer super-frame, it will read in the contents of the Tx TTB-0 Register (Address = 0x38)
and insert this value into the TR byte-field of this very first Outbound E3 frame. When the Transmit E3 Framer
is generating the very next E3 frame (e.g., the second E3 frame, within the Trail Trace Buffer super-frame), it
will read in the contents of the Tx TTB-1 register (Address = 0x39) and insert this value into the TR byte-field of
this Outbound E3 frame. As the Transmit E3 Framer block is creating each subsequent E3 frame, within this
Trail Trace Buffer super frame, it will continue to increment to the very next Transmit Trail Trace Buffer register.
The Transmit E3 Framer block will then read in the contents of this particular Transmit Trail Trace Buffer regis-
ter (Tx TTB-n) and insert this value into the TR byte-field of the very next Outbound E3 frame. After the Trans-
mit E3 Framer block has created the 16th E3 frame, within a given Trail Trace Buffer super-frame (e.g., it has
read in the contents of Tx TTB-15 register and has inserted this value into the TR byte of the 16th E3 frame), it
will begin to create a new Trail Trace Buffer super-frame, by reading the contents of the Tx TTB-0 register, and
repeating the above-mentioned procedure.
The contents of the Tx TTB-0 register will typically be of the form [1, C6, C5, C4, C3, C2, C1, C0]. The “1” in
the MSB (Most Significant bit) position of this byte is used to designate that this octet is the frame-start marker
(e.g., is the first of the 16 TR bytes, within a Trail Trace Buffer super-frame). The remaining Trail Trace Buffer
registers (TxTTB-1 through TxTTB-15) will typically contain a “0” in their MSB positions. The remaining bits
within the Tx TTB-0 register C6 through C0 are the CRC-7 bits calculated over the contents of all 16 TR bytes,
within the previous Trail Trace Buffer super-frame. The contents of the remaining Trail Trace Buffer registers
(e.g., Tx TTB-1 through Tx TTB-15) will typically contain the 15 ASCII characters required for the E.164 num-
bering format.
NOTES:
1. The XRT72L52 Framer IC will not compute the CRC-7 value, to be written into the Tx TTB-0 register. The user’s
system must compute this value prior to writing it into the Tx TTB-0 register.
2. The user, when writing data into the Tx TTB registers, must take care to insure that only the Tx TTB-0 register con-
tains an octet with a “1” in the MSB (most significant bit) position. All remaining Tx TTB registers (e.g., Tx TTB-1
through Tx TTB-15) must contain octets with a “0” in the MSB position. The reason for this cautionary note is pre-
sented in Section 6.1.1.3.
6.2.5 The Transmit E3 Line Interface Block
The XRT72L52 Framer IC is a digital device that takes E3 payload and overhead bit information from some ter-
minal equipment, processes this data and ultimately, multiplexes this information into a series of Outbound E3
frames. However, the XRT72L52 Framer IC lacks the current drive capability to be able to directly transmit this
E3 data stream through some transformer-coupled coax cable with enough signal strength for it to be received
390