XR72L52 Datasheet, PDF (414/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
4. Finally, it will begin transmitting the contents of this LAPD Message frame via either the NR or GC bytes
within each Outbound E3 frame.
5. Once the LAPD Transmitter has completed its transmission of this LAPD Message frame (to the Remote
Terminal Equipment), the XRT72L52 Framer IC will generate the Completion of Transmission of a LAPD
Message Interrupt to the Microcontroller/Microprocessor. Once the XRT72L52 Framer IC generates this
interrupt, it will do the following.
• Assert the Interrupt Output pin (Int) by toggling it "Low".
• Set Bit 0 (TxLAPD Interrupt Status) within the TxE3 LAPD Status and Interrupt Register, to “1” as illustrated
below.
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
TXDL Start
BIT 2
TXDL Busy
R/W
RO
0
0
BIT 1
TxLAPD
Interrupt
Enable
R/W
0
BIT 0
TxLAPD
Interrupt
Status
RUR
1
The purpose of this interrupt is to alert the Microcontroller/MIcroprocessor that the LAPD Transmitter has com-
pleted its transmission of a given LAPD (or PMDL) Message, and is now ready to transmit the next PMDL Mes-
sage, to the Remote Terminal Equipment.
6.3 THE RECEIVE SECTION OF THE XRT72L52 (E3 MODE OPERATION)
When the XRT72L52 has been configured to operate in the E3 Mode, the Receive Section of the XRT72L52
consists of the following functional blocks.
• Receive LIU Interface block
• Receive HDLC Controller block
• Receive E3 Framer block
• Receive Overhead Data Output Interface block
• Receive Payload Data Output Interface block
Figure 173 presents a simple illustration of the Receive Section of the XRT72L52 Framer IC.
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