XR72L52 Datasheet, PDF (224/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FIGURE 72. FLOW DIAGRAM DEPICTING HOW THE RECEIVE FEAC PROCESSOR FUNCTIONS
SSTTAARRTT
11
EENNAABBLLEETTHHEE““FFEEAACCRREEMMOOVVAALLAANNDD
“V“VAALLIDIDAATTIOIONN””ININTTEERRRRUUPPTTSS. _.
TThhisisisisacaccocommpplilsihshededbbyywwrirtiitningg“x“xxxxxxx11001100””inintotoththee
“R“RxDxDSS33FFEEAACCInItnetrerrurputp/tS/StattautsusRRegeigsitsetrer(A(Addddrersesss==00xx1177) ₎
RREECCEEIVIVEEFFEEAACCPPRROOCCEESSSSOORRBBEEGGININSSRREEAADDININGGININ
TTHHEEFFEEAACCBBITIT-F-FIEIELLDDSS(O(OFFININCCOOMMININGGDDSS33FFRRAAMMEESS) ₎
TThheeRReceecievieveFFEEAACCPProrcoecsessosrorchcehcekcsksfofrorththee“F“FEEAACCFFrarmaminingg
AAlilgignnmmenetn”t”paptattetrenrnoof _{f“0“011111111111100”.”.}
HHasasththisis
sasmameeFFEEAACC
CCodoedeWWorodrdbbeeenen
YES
RReceecievivededinin88oouut _{tofofthtehelalsatst}
1010FFEEAACCMMesessasgaege
RReceecpetpitoinons?s?
NO
GGEENNEERRAATTEE““FFEEAACC
VVAALLIDIDAATTIOIONN””ININTTEERRRRUUPPTT
ININVVOOKKEE““FFEEAACCVVAALLIDIDAATTIOIONN””
ININTTEERRRRUUPPTTSSEERRVVICICEERROOUUTTININEE. _.
IsIsththee
“F“FEEAACCFFrarmaminingg
AAlilgignnmmenent”tp”patattetrenrn
NO
pprerseesnent _{tininthteheFFEEAACC NO}
CChahnannenlel
??
YES
RREEAADDININTTHHEE“6“-6B-BITITFFEEAACCCCOODDEEWWOORRDD””
TThhe _{e66-b-bititFFEEAACCCCooddeeWWoordrdimimmmedediaitaetleylyfofolllolowws sththee“F“FEEAACC}
FFrarmamininggAAlilgignnmmenent”t”PPatattetrenrn. _.
HHasasaaFFEEAACC
CCodoedeWWorodrd(o(tohtehrerththanan
thtehelalsatst“V“ValaildiadtaetdedCCoodedeWWorodr)d)
bbeeenenRReceecievievdedinin33oouut _{tofofththeelalsatst}
1010FFEEAACCMMesessasgaege
RReceecpetpitoinons?s?
11
YES
GGEENNEERRAATTEE““FFEEAACC
RREEMMOOVVAALL””ININTTEERRRRUUPPTT
11
ININVVOOKKEE“F“FEEAACCRREEMMOOVVAALL””
ININTTEERRRRUUPPTTSSEERRVVICICEERROOUUTTININEE. _.
NOTES:
1. The white (e.g., unshaded) boxes reflect tasks that the user’s system must perform in order to configure the
Receive FEAC Processor to receive FEAC messages.
2. A brief description of the steps that must exist within the FEAC Validation and FEAC Removal Interrupt Service
Routines exists in Section 4.3.3
4.3.3.2 The Message Oriented Signaling (e.g., LAP-D) Processing via the Receive DS3 HDLC Con-
troller block
The LAPD Receiver (within the Receive DS3 HDLC Controller block) allows the user to receive PMDL messag-
es from the remote terminal equipment, via the inbound DS3 frames. In this case, the inbound message bits
will be carried by the 3 DL bit-fields of F-Frame 5, within each DS3 M-Frame. The remote LAPD Transmitter
will transmit a LAPD Message to the Near-End Receiver via these three bits within each DS3 Frame. The
LAPD Receiver will receive and store the information portion of the received LAPD frame into the Receive
LAPD Message Buffer, which is located at addresses: 0xDE through 0x135 within the on-chip RAM. The
LAPD Receiver has the following responsibilities.
• Framing to the incoming LAPD Messages
• Filtering out stuffed “Zeros” (Between the two flag sequence bytes, 0x7E)
• Storing the Frame Message into the Receive LAPD Message Buffer
• Perform Frame Check Sequence (FCS) Verification
• Provide status indicators for
End of Message (EOM)
208