XR72L52 Datasheet, PDF (34/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
PIN DESCRIPTION
PIN #
143
PIN NAME
TxOHClk[0]
144
TxOHFrame[0]/
TxHDLCClk[0]
145
RxOHEnable[0]/
RxHDLCDat5[0]
146
RxOHFrame[0]/
RxHDLCDat4[0]
147
RxOHClk[0]/
RxHDLCClk[0]
148
RxOH[0]/
RxHDLCDat6[0]
149
GND
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
TYPE
O
O
O
O
O
O
****
DESCRIPTION
Transmit Overhead Clock:
This output signal serves two purposes:
1. The Transmit Overhead Data Input Interface block provides a rising clock
edge on this signal one bit-period prior to the start of the instant that the Trans-
mit Overhead Data Input Interface block is processing an overhead bit.
2. The Transmit Overhead Data Input Interface samples the data at the TxOH
input pin on the falling edge of this clock signal, provided that the TxOHIns input
pin is "High".
NOTE: The Transmit Overhead Data Input Interface block supplies a clock edge
for all overhead bits within the DS3 or E3 frame via the TxOHClk output signal.
This includes those overhead bits that the Transmit Overhead Data Input Inter-
face does not accept from the Terminal Equipment.
Transmit Overhead Framing Pulse:
This output pin pulses "High" when the Transmit Overhead Data Input Interface
block is expecting the first Overhead bit within a DS3 or E3 frame to be applied
to the TxOH input pin.
This pin is "High" for one clock period of TxOHClk.
Transmit HDLC Output Clock:
When the HDLC controller is on, TxHDLCDat is updated by the XRT72L52 with
this clock signal.
Receive Overhead Enable Indicator:
The XRT72L52 asserts this output signal for one RxOutClk period when it is
safe for the Terminal Equipment to sample the data on the RxOH output pin.
Receive HDLC Data Output - 5:
This pin contains bit 5 RxHDLC data when the HDLC controller is on.
Receive Overhead Frame Boundary Indicator:
This output pin pulses "High" whenever the Receive Overhead Data Output
Interface block outputs the first overhead bit or nibble of a new DS3 or E3 frame.
Receive HDLC Data Output - 4:
This pin contains bit 4 RxHDLC data when the HDLC controller is on.
Receive Overhead Output Clock Signal:
The XRT72L52 outputs the Overhead bits within the incoming DS3 or E3 frames
via the RxOH output pin upon the falling edge of this clock signal.
The user's data link equipment should use the rising edge of this clock signal to
sample the data on both the RxOH and RxOHFrame output pins.
NOTE: This clock signal is always active.
Receive HDLC Output Clock:
When the HDLC controller is on, RxHDLCDat is updated by the XRT72L52 on
this clock signal.
Receive Overhead Output Port:
All overhead bits which are received via the Receive Section of the Framer IC
are output via this output pin upon the rising edge of RxOHClk.
Receive HDLC Data Output - 6:
This pin contains bit 6 RxHDLC data when the HDLC controller is on.
Ground
18