XR72L52 Datasheet, PDF (77/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
The Receive FEAC Processor will validate a new FEAC message, once that message has been received in 8
out of 10 most recently received FEAC Messages.
NOTE: For more information on this bit-field and the Receive FEAC Processor, refer to Section 4.3.3.1.
2.3.2.15 Receive DS3 LAPD Control Register
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
RxLAPD
Enable
RxLAPD
Interrupt
Enable
RxLAPD
Interrupt
Status
RO
RO
RO
RO
RO
R/W
R/W
RUR
0
0
0
0
0
0
0
0
Bit 2 RxLAPD Enable
This Read/Write bit-field permits the user to enable or disable the LAPD Receiver. The LAPD Receiver MUST
be enabled before it can begin to receive and process any LAPD Message frames from the incoming DS3 data
stream.
Writing a "0" to this bit-field disables the LAPD Receiver (the default condition). Writing a "1" to this bit-field en-
ables the LAPD Receiver.
Bit 1 RxLAPD (Message Frame Reception Complete) Interrupt Enable
This Read/Write bit-field permits the user to enable or disable the LAPD Message Frame Reception Complete
interrupt. If this interrupt is enabled, then the channel generates this interrupt to the local µP, once the last bit
of a LAPD Message frame has been received and the PMDL message has been extracted and written into the
Receive LAPD Message buffer.
Writing a "0" to this bit-field disables this interrupt (the default condition). Writing a "1" to this bit-field enables
this interrupt.
Bit 0 RxLAPD (Message Reception Complete) Interrupt Status
This Reset-upon-Read bit-field indicates whether or not the LAPD Message Reception Complete interrupt has
occurred since the last read of this register. The LAPD Message Reception Complete interrupt will occur once
the LAPD Receiver has received the last bit of a complete LAPD Message frame, extracted the PMDL mes-
sage from this LAPD Message frame and has written this (PMDL) message frame into the Receive LAPD Mes-
sage buffer. The purpose of this interrupt is to notify the local µP that the Receive LAPD Message buffer con-
tains a new PMDL message, that needs to be read and/or processed.
A "0" in this bit-field indicates that the LAPD Message Reception Complete interrupt has NOT occurred since
the last read of this register. A "1" in this bit-field indicates that the LAPD Message Reception Complete inter-
rupt has occurred since the last read of this register.
NOTE: For more information on the LAPD Receiver, refer to Section 4.3.3.2.
2.3.2.16 Receive DS3 LAPD Status Register
RXDS3 LAPD STATUS REGISTER (ADDRESS = 0X19)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
RxAbort
RxLAPDType[1:0}
RxCR Type RxFCS Error End of Flag Present
Message
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
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