XR72L52 Datasheet, PDF (358/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
6.0 E3/ITU-T G.832 OPERATION OF THE XRT72L52
The XRT72L52 can be configured to operate in the E3/ITU-T G.832 Mode by writing a “0” into bit-field 6
and a “1” into bit-field 2, within the Framer Operating Mode register, as illustrated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local Loop-back
DS3/E3*
Internal
LOS Enable
RESET
Interrupt Frame Format
Enable Reset
TimRefSel[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
0
x
0
x
1
x
x
6.1 DESCRIPTION OF THE E3, ITU-T G.832 FRAMES AND ASSOCIATED OVERHEAD BYTES
The E3, ITU-T G.832 Frame contains 537 bytes, of which 7 bytes are overhead and the remaining 530 bytes
are payload bytes.
These 537 octets are arranged in 9 rows of 60 columns each, except for the last three rows which contain only
59 columns. The frame repetition rate for this type of E3 frame is 8000 times per second, thereby resulting in
the standard E3 bit rate of 34.368 Mbps. Figure 142 presents an illustration of the E3, ITU-T G.832 Frame For-
mat.
FIGURE 142. ILLUSTRATION OF THE E3, ITU-T G.832 FRAMING FORMAT.
FA1
FA2
EM
TR
MA
NR
GC
60 Columns
530 Octet Payload
9 Rows
1 Byte
59 Bytes
6.1.1 Definition of the Overhead Bytes
The seven (7) overhead bytes are shown in Figure 142, as FA1, FA2, EM, TR, MA, NR and GC. Each of these
Overhead Bytes are further defined below.
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