XR72L52 Datasheet, PDF (465/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
current state of the AIS defect by reading the state of Bit 3 (RxAIS) within the Rx E3 Configuration and Sta-
tus Register - 2, as illustrated below.
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)
BIT 7
Rx LOF Algo
BIT 6
RxLOF
R/W
RO
X
X
BIT 5
RxOOF
RO
X
BIT 4
RxLOS
RO
X
BIT 3
RxAIS
RO
X
BIT 2
RxPld Unstab
RO
X
BIT 1
Rx
TMark
RO
X
BIT 0
RxFERF
RO
X
If the AIS Condition is TRUE
1. It should begin transmitting the FERF indication to the Remote Terminal Equipment. The XRT72L52
Framer IC automatically supports this action via the FERF-upon-AIS feature.
If the AIS Condition is FALSE
2. It should cease transmitting the FERF indication to the Remote Terminal Equipment. The XRT72L52
Framer IC automatically supports this action via the FERF-upon-AIS feature.
6.3.6.2.6 The Change in Trail Trace Buffer Message Interrupt
If the Change in Trail Trace Buffer Message Interrupt has been enabled, then the XRT72L52 Framer IC will
generate an interrupt any time the Receive E3 Framer block receives a different Trail Trace Buffer message,
then it has previously read in.
Enabling and Disabling the Change in Trail Trace Buffer Message Interrupt.
The user can enable or disable the Change in Trail Trace Buffer Message interrupt by writing the appropriate
value into Bit 6 (TTB Change Interrupt Enable) within the Rx E3 Interrupt Enable Register - 2, as indicated be-
low.
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
BIT 7
Not Used
RO
0
BIT 6
TTB
Change
Interrupt
Enable
R/W
0
BIT 5
Not Used
RO
0
BIT 4
FEBE
Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
X
BIT 2
BIP-8
Error Interrupt
Enable
R/W
0
BIT 1
Framing
Byte Error
Interrupt
Enable
R/W
0
BIT 0
RxPld
Mis
Interrupt
Enable
R/W
0
Writing a “1” into this bit-field enables the Change in Trail Trace Buffer Message Interrupt. Conversely, writing
a “0” into this bit-field disables the Change in Trail Trace Buffer Message Interrupt.
Servicing the Change in Trail Trace Buffer Message Interrupt
Whenever the XRT72L52 Framer IC generates this interrupt, it will do the following.
• It will assert the Interrupt Request output pin (Int) by driving it "Low".
• It will set Bit 6 (TTB Change Interrupt Status), within the Rx E3 Interrupt Status Register - 2, as indicated
below.
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