XR72L52 Datasheet, PDF (223/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
Not Used
BIT 6
Not Used
BIT 5
Not Used
RO
RO
RO
X
X
X
BIT 4
FEAC
Valid
RO
1
BIT 3
RxFEAC
Remove
Interrupt
Enable
R/W
X
BIT2
RxFEAC
Remove
Interrupt
status
RUR
0
BIT 1
RxFEAC
Valid
Interrupt
Enable
R/W
1
BIT 0
RxFEAC
Valid
Interrupt
Status
RUR
1
The bit-format of the Rx DS3 FEAC register is presented below. It is important to note that the last validated
FEAC code word will be written into the shaded bit-fields below.
RX DS3 FEAC REGISTER (ADDRESS = 0X16)
BIT 7
Not Used
RO
0
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
RxFEAC [5]
RO
d5
RxFEAC [4]
RO
d4
RxFEAC [3]
RO
d3
RxFEAC [2]
RO
d2
RxFEAC [1]
RO
d1
RxFEAC [0]
RO
d0
BIT 0
Not Used
RO
0
The purpose of generating an interrupt to the µP, upon FEAC Code Word Validation is to inform the local µP
that the Framer has a newly received FEAC message that needs to be read. The local µP would read-in this
FEAC code word from the Rx DS3 FEAC Register (Address = 0x16).
FEAC Code Removal
After the 10th transmission of a given FEAC code word, the remote terminal equipment may proceed to trans-
mit a different FEAC code word. When the Receive FEAC processor detects this occurrence, it must Remove
the FEAC codeword that is presently residing in the Rx DS3 FEAC Register. The Receive FEAC Processor
will remove the existing FEAC code word when it detects that 3 (or more) out of the last 10 received FEAC
codes are different from the latest validated FEAC code word. The Receive FEAC Processor will inform the lo-
cal µP/µC of this removal event by generating a Rx FEAC Removal interrupt, and asserting the RxFEAC Re-
move Interrupt Status bit in the Rx DS3 Interrupt Enable/Status Register, as depicted below.
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
Not Used
BIT 6
Not Used
BIT 5
Not Used
RO
RO
RO
X
X
X
BIT 4
FEAC
Valid
RO
0
BIT 3
RxFEAC
Remove
Interrupt
Enable
R/W
1
BIT2
RxFEAC
Remove
Interrupt
status
RUR
1
BIT 1
RxFEAC
Valid
Interrupt
Enable
R/W
X
BIT 0
RxFEAC
Valid
Interrupt
Status
RUR
0
Additionally, the Receive FEAC processor will also denote the removal event by setting the FEAC Valid bit-field
(Bit 4), within the Rx DS3 FEAC Interrupt Enable/Status Register to 0, as depicted above.
The description of Bits 0 through 3 within this register, all support Interrupt Processing, and will therefore be
presented in Section 4.3.6. Figure 72 presents a flow diagram depicting how the Receive FEAC Processor
functions.
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