XR72L52 Datasheet, PDF (118/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
frame. Consequently, to insure errors are not injected into the FA1 octet of the outbound E3 frames, the con-
tents of this register must be set to all “0’s” (the default value).
2.3.6.24 Transmit E3 FA2 Byte Error Mask Register (E3, ITU-T G.832)
TXE3 FA2 ERROR MASK REGISTER (ADDRESS = 0X49)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxFA2_Error_Mask_Byte[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
This Read/Write bit-field permits the user to insert errors into the Framing Alignment octet, FA2 of each out-
bound E3 frame. The user may wish to do this for equipment testing purposes. Prior to transmission, the
Transmit DS3/E3 Framer block reads in the FA2 byte, and performs an XOR operation with it and the contents
of this register. The results of this operation are written back into the FA2 octet position, in each outbound E3
frame. Consequently, to insure errors are not injected into the FA2 octet of the outbound E3 frames, the con-
tents of this register must be set to all "0’s" (the default value).
2.3.6.25 Transmit E3 BIP-8 Error Mask Register (E3, ITU-T G.832)
TXE3 BIP-8 ERROR MASK REGISTER (ADDRESS = 0X4A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxBIP-8_Error_Mask_Byte[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
This Read/Write bit-field permits the user to insert errors into EM (Error Monitor) octet of each outbound E3
frame. The user may wish to do this for equipment testing purposes. Prior to transmission, the Transmit DS3/
E3 Framer block reads in the EM byte, and performs an XOR operation with it and the contents of this register.
The results of this operation are written back into the EM octet position, in each outbound E3 frame. Conse-
quently, to insure errors are not injected into the EM octet of the outbound E3 frames, the contents of this reg-
ister must be set to all "0’s" (the default value).
2.3.7 Transmit E3 Framer Configuration Registers (ITU-T G.751)
2.3.7.1 Transmit E3 Configuration Register (ITU-T G.751)
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Tx
BIP-4
Enable
TxASourceSel[1:0]
TxNSourceSel[1:0]
Tx AIS
Enable
Tx LOS
Enable
Tx FAS
Source
Select
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 - TxBIP-4 Enable
This Read/Write bit-field permits the user to configure the Transmit Section of the Channel, to compute an in-
sert the BIP-4 value into each outbound E3 frame.
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