XR72L52 Datasheet, PDF (9/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
I/O CONTROL REGISTER (ADDRESS = 0X01)............................................................................................ 197
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X52) ................................... 197
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X53) .................................... 198
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ..................................................... 198
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)....................................................................... 199
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ..................................................... 199
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ..................................................... 200
RX DS3 STATUS REGISTER (ADDRESS = 0X11)....................................................................................... 201
RX DS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ..................................................................... 201
RXDS3 STATUS REGISTER (ADDRESS = 0X11)........................................................................................ 202
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ...................................................................... 202
PMON PARITY ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X54)............................................ 203
PMON PARITY ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X55)............................................. 203
Figure 70. A Simple Illustration of the Locations of the Source, Mid-Network and Sink Terminal Equipment (for CP-Bit
Processing).................................................................................................................................................... 204
Figure 71. Illustration of the Presumed Configuration of the Mid-Network Terminal Equipment .................................. 205
4.3.3 The Receive HDLC Controller Block .................................................................................................... 205
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17).............................................. 207
RX DS3 FEAC REGISTER (ADDRESS = 0X16) ......................................................................................... 207
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17).............................................. 207
Figure 72. Flow Diagram depicting how the Receive FEAC Processor Functions ....................................................... 208
Figure 73. LAPD Message Frame Format.................................................................................................................... 209
RX DS3 LAPD CONTROL REGISTER (ADDRESS = 0X18).......................................................................... 210
RX DS3 LAPD STATUS REGISTER (ADDRESS = 0X19) ............................................................................ 210
TABLE 37: THE RELATIONSHIP BETWEEN RXLAPDTYPE[1:0] AND THE RESULTING LAPD MESSAGE TYPE AND SIZE ........... 210
Figure 74. Flow Chart depicting the Functionality of the LAPD Receiver ..................................................................... 212
4.3.4 The Receive Overhead Data Output Interface ..................................................................................... 212
Figure 75. The Receive Overhead Output Interface block ........................................................................................... 213
TABLE 38: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
214
Figure 76. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface Block (Method 1)214
TABLE 39: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXOHFRAME WAS LAST
SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN ................... 215
Figure 77. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method 1). ........ 217
TABLE 40: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
(METHOD 2) .................................................................................................................................................... 217
Figure 78. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface (Method 2) .... 218
TABLE 41: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES ((SINCE RXOHFRAME WAS LAST
SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN ................... 219
Figure 79. Illustration of the signals that are output via the Receive Overhead Data Output Interface block (for Method 2).
221
4.3.5 The Receive Payload Data Output Interface........................................................................................ 221
Figure 80. The Receive Payload Data Output Interface block...................................................................................... 221
TABLE 42: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK
222
Figure 81. The XRT72L52 DS3/E3 Framer IC being interfaced to the Receive Terminal Equipment (Serial Mode Operation)
224
Figure 82. An Illustration of the behavior of the signals between the Receive Payload Data Output Interface block of the
XRT72L52 and the Terminal Equipment (Serial Mode Operation) ................................................................ 225
Figure 83. The XRT72L52 DS3/E3 Framer IC being interfaced to the Receive Section of the Terminal Equipment (Nibble-
Parallel Mode Operation)............................................................................................................................... 226
Figure 84. An Illustration of the Behavior of the signals between the Receive Payload Data Output Interface Block of the
XRT72L52 and the Terminal Equipment (Nibble-Mode Operation). .............................................................. 227
4.3.6 Receive Section Interrupt Processing .................................................................................................. 227
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ....................................................................... 228
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ...................................................................... 228
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ...................................................................... 229
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10)........................................................... 229
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ...................................................................... 230
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ...................................................................... 230
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10)........................................................... 230
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