XR72L52 Datasheet, PDF (314/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FIGURE 124. THE STATE MACHINE DIAGRAM FOR THE RECEIVE E3 FRAMER E3 FRAME ACQUISITION/MAINTENANCE
ALGORITHM
FAS
Pattern
Search
FAS pattern is
detected once
FAS
Pattern
Verification
FAS Pattern is
not detected
LOF
Condition
FAS Pattern is
verified once
8 or 24 framing periods
of operating in the
OOF condition
(user-selectable)
OOF
Condition
3 consecutive
Valid Frames
4 consecutive
In-valid Frames
In Frame
Frame Maintenance
Mode
FIGURE 125. ILLUSTRATION OF THE E3, ITU-T G.751 FRAMING FORMAT
1
1 0 1 1 1 2
F r a m e
A lig n m e n t _AN
S ig n a l
3 8 4 3 8 5
7 6 87 6 9 1 1 5 21 1 5 3 1 5 3 2
1 5 3 6
D a ta
D a ta
D a ta
B I P -4
D a ta _{ifS e le c te d}
F r a m in g A lig n m e n tS ig n a lP a tte r n = 1 1 1 1 0 1 0 0 0 0
When the Receive E3 Framer block detects the FAS pattern, it will then transition over to the FAS Pattern Ver-
ification state, per Figure 125.
The FAS Pattern Verification State
298