XR72L52 Datasheet, PDF (240/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FIGURE 81. THE XRT72L52 DS3/E3 FRAMER IC BEING INTERFACED TO THE RECEIVE TERMINAL EQUIPMENT
(SERIAL MODE OPERATION)
Rx_DS3_Clock_In
DS3_Data_In
Rx_Start_of_Frame
Rx_DS3_OH_Ind
44.736MHz
Clock Signal
RxClk
RxSer
RxLineClk
RxFrame
44.736MHz
Clock Source
RxOHIns
Terminal Equipment
Receive Payload Section
DS3 Framer
Required Operation of the Terminal Equipment
The XRT72L52 will update the data on the RxSer output pin, upon the rising edge of RxClk. However, be-
cause the rising edge of RxClk to data delay is between 14ns to 16ns, the Terminal Equipment should sample
the data on the RxSer output pin (or the DS3_Data_In pin at the Terminal Equipment) upon the rising edge of
RxClk. This will still permit the Terminal Equipment with a RxSer to RxClk set-up time of approximately 6ns
and a hold time of 14 to 16ns. As the Terminal Equipment samples RxSer with each rising edge of RxClk it
should also be sampling the following signals.
• RxFrame
• RxOHInd
The Need for sampling RxFrame
The XRT72L52 will pulse the RxFrame output pin "High" coincident with it driving the very first bit of a given
DS3 frame onto the RxSer output pin. If knowledge of the DS3 Frame Boundaries is important for the opera-
tion of the Terminal Equipment, then this is a very important signal for it to sample.
The Need for sampling RxOHInd
The XRT72L52 will indicate that it is currently driving an overhead bit onto the RxSer output pin, by pulsing the
RxOHInd output pin "High". If the Terminal Equipment samples this signal "High", then it should know that the
bit, that it is currently sampling via the RxSer pin is an overhead bit and should not be processed.
The Behavior of the Signals between the Receive Payload Data Output Interface block and the Terminal
Equipment
The behavior of the signals between the XRT72L52 and the Terminal Equipment for DS3 Serial Mode Opera-
tion is illustrated in Figure 82.
224