XR72L52 Datasheet, PDF (58/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FIGURE 24. MICROPROCESSOR INTERFACE TIMING - INTEL-TYPE PROGRAMMED I/O WRITE OPERATION
ALE_AS
A[8:0]
CS
D[7:0]
RD_DS
W R_R/W
RDY_DTCK
Address of Target Register
Data to be W ritten
2.2.2.1.2 Programmed I/O Access in the Motorola Mode
If the XRT72L52 DS3/E3 Framer is interfaced to a Motorola-type µC/µP (e.g., the MC680X0 family, etc.), it
should be configured to operate in the Motorola mode by tying the MOTO pin to “High”.
The Motorola Mode Read Cycle
Whenever a Motorola-type µC/µP wishes to read the contents of a register or some location within the Receive
LAPD Message.
1. Place the address of the target register or buffer location on the Address Bus input pins, A[8:0].
2. At the same time, the Address Decoding circuitry (within the user's system) should assert the CS (Chip
Select) input pin of the Framer, by toggling it "Low". This action enables further communication between
the µC/µP and the Framer Microprocessor Interface block.
3. Assert the ALE_AS (Address-Strobe) input pin by toggling it “Low”. This step enables the Address Bus
input drivers within the Microprocessor Interface Block of the Framer IC.
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate Address Setup time),
the µC/µP should toggle the ALE_AS input pin "High". This step causes the Framer to latch the contents
of the Address Bus into its internal circuitry. At this point, the address of the register or buffer location has
now been selected.
5. The µC/µP should indicate that this cycle is a Read cycle by setting the WR_R/W (R/W) input pin "High".
6. Next the µC/µP should initiate the current bus cycle by toggling the RD_DS (Data Strobe) input pin "Low".
This step enables the bi-directional data bus output drivers within the XRT72L52 DS3/E3 Framer. At this
point, the bi-directional data bus output drivers will proceed to drive the contents of the Address register
onto the bi-directional data bus, D[7:0].
7. After some settling time, the data on the bi-directional data bus will stabilize and can be read by the µC/µP.
The XRT72L52 DS3/E3 Framer will indicate that this data can be read by asserting the RDY_DTCK
(DTACK) signal.
8. After the µC/µP detects the RDY_DTCK signal, it terminates the Read Cycle by toggling the RD_DS input
pin "High".
Figure 25 presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals dur-
ing a Motorola-type Programmed I/O Read Operation.
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