XR72L52 Datasheet, PDF (458/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
FIGURE 199. ILLUSTRATION OF THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE OVERHEAD DATA OUTPUT INTER-
FACE BLOCK (FOR METHOD 2).
Terminal Equipment Signals
RxOutClk
Rx_E3_Clock_In
E3_Data_In[3:0]
Rx_Start_of_Frame
Overhead Nibble [0]
Overhead Nibble [1]
Rx_E3_OH_Ind
XRT72L5x Receive Payload Data I/F Signals
RxOutClk
RxClk
RxNib[3:0]
RxFrame
Overhead Nibble [0]
Overhead Nibble [1]
RxOH_Ind
E3 Frame Number N
Note: RxFrame pulses high to denote
E3 Frame Boundary.
E3 Frame Number N + 1
Recommended Sampling Edge of Terminal
Equipment
6.3.6 Receive Section Interrupt Processing
The Receive Section of the XRT72L52 can generate an interrupt to the MIcrocontroller/Microprocessor for the
following reasons.
• Change in Receive LOS Condition
• Change in Receive OOF Condition
• Change in Receive LOF Condition
• Change in Receive AIS Condition
• Change in Receive FERF Condition
• Change of Framing Alignment
• Change in Receive Trail Trace Buffer Message
• Detection of FEBE (Far-End Block Error) Event
• Detection of BIP-8 Error
• Detection of Framing Byte Error
• Detection of Payload Type Mismatch
• Reception of a new LAPD Message
6.3.6.1 Enabling Receive Section Interrupts
The Interrupt Structure within the XRT72L52 contains two hierarchical levels.
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