XR72L52 Datasheet, PDF (59/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
FIGURE 25. MICROPROCESSOR INTERFACE TIMING - MOTOROLA-TYPE PROGRAMMED I/O READ OPERATION
ALE_AS
A[8:0]
CS
D[7:0]
RD_DS
W R_R/W
RDY_DTCK
Address of Target Register
Not Valid
Valid Data
The Motorola Mode Write Cycle
Whenever a Motorola-type µC/µP wishes to write a byte or word of data into a register or buffer location, it
should do the following.
1. Assert the ALE_AS input pin by toggling it "Low". This step enables the Address Bus input drivers.
2. Place the address of the target register or buffer location on the Address Bus input pins, A[8:0].
3. While the µC/µP is placing this address value onto the Address Bus, the Address-Decoding circuitry (within
the user's system) should assert the CS input pins of the Framer by toggling it "Low". This step enables
further communication between the µC/µP and the Framer Microprocessor Interface block.
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate Address Setup time),
the µC/µP should toggle the ALE_AS input pin "High". This step causes the Framer to latch the contents
of the Address Bus into its own circuitry. At this point, the Address of the register or buffer location has
now been selected.
5. Further, the µC/µP should indicate that this current bus cycle is a Write operation by toggling the WR_R/W
(R/W) input pin "Low".
6. The µC/µP should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus, D[7:0].
7. Next, the µC/µP should initiate the bus cycle by toggling the RD_DS input pin "Low". When the XRT72L52
DS3/E3 Framer senses that the WR_R/W (R/W) input pin is "High" and the RD_DS input pin has toggled
"Low", it will enable the input drivers of the bi-directional data bus, D[7:0].
8. After waiting the appropriate time for this newly placed data to settle on the bi-directional data bus (e.g., the
Data Setup time) the Framer will assert the RDY_DTCK output signal.
9. After the µC/µP detects the RDY_DTCK signal, the µC/µP should toggle the RD_DS input pin "High" and
terminates the Write cycle.
Figure 26 presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals, dur-
ing a Motorola-type Programmed I/O Write Operation.
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