XR72L52 Datasheet, PDF (102/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
2.3.5.2 Transmit DS3 FEAC Configuration & Status Register
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
Tx FEAC
Interrupt
Enable
TxFEAC
Interrupt
Status
TxFEAC
Enable
TxFEAC
GO
TxFEAC
Busy
RO
RO
RO
R/W
RUR
R/W
R/W
RO
0
0
0
0
0
0
0
0
Bit 4 - Tx FEAC Interrupt Enable
This Read-Write bit-field permits the user to enable or disable the Transmit FEAC Interrupt.
Setting this bit-field to “0” disables this interrupt.
Conversely, setting this bit-field to “1” enables this interrupt.
Bit 3 - TxFEAC Interrupt Status
This Reset-upon-Read bit-field indicates whether or not the FEAC Message Transmission Complete interrupt
has occurred since the last read of this register. This interrupt will occur once the Transmit FEAC Processor
has finished its 10th transmission of the 16 bit FEAC Message (6 bit FEAC Code word + 10 framing bits). The
purpose of this interrupt is to let the local µP know that the Transmit FEAC Processor has completed its trans-
mission of its latest FEAC Message and is now ready to transmit another FEAC Message.
If this bit-field is "0", then the FEAC Message Transmission Complete interrupt has NOT occurred since the
last read of this register.
If this bit-field is “1”, then the FEAC Message Transmission Complete interrupt has occurred since the last read
of this register.
NOTE: For more information on the Transmit FEAC Processor, refer to Section 4.2.3.1.
Bit 2 - TxFEAC Enable
This Read/Write bit-field allows the user to enable or disable the Transmit FEAC Processor. The Transmit
FEAC Processor will NOT function until it has been enabled.
Writing a "0" to this bit-field disables the Transmit FEAC Processor. Writing a "1" to this bit-field enables the
Transmit FEAC Processor.
Bit 1 - TxFEAC Go
This bit-field allows the user to invoke the Transmit FEAC Message command. Once this command has been
invoked, the Transmit FEAC Processor will do the following:
• Encapsulate the 6 bit FEAC code word, from the Tx DS3 FEAC Register (Address = 0x32) into a 16 bit FEAC
Message
• Serially transmit this 16-bit FEAC Message to the far-end receiver via the outbound DS3 data-stream, recur-
sively. After the 10^th transmission, generate the TxFEAC complete interrupt and continue transmitting.
NOTE: For more information on the Transmit FEAC Processor, refer to Section 4.2.3.1.
Bit 0 - TxFEAC Busy
This Read-Only bit-field allows the local µP to poll and determine if the Transmit FEAC Processor has complet-
ed its 10th transmission of the 16-bit FEAC Message. This bit-field will contain a "1", if the Transmit FEAC Pro-
cessor is still transmitting the FEAC Message. This bit-field will toggle to "0", once the Transmit FEAC Proces-
sor has completed its 10th transmission of the FEAC Message.
NOTE: For more information on the Transmit FEAC Processor, refer to Section 4.2.3.1.
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