XR72L52 Datasheet, PDF (12/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
be updated on the rising edge of TxLineClk .................................................................................................. 288
Figure 114. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are configured to
be updated on the falling edge of TxLineClk ................................................................................................. 288
5.2.6 Transmit Section Interrupt Processing ................................................................................................. 288
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)........................................................................289
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ........................................................289
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ........................................................290
5.3 THE RECEIVE SECTION OF THE XRT72L52 (E3 MODE OPERATION) .................................................................. 290
Figure 115. The XRT72L52 Receive Section configured to operate in the E3 Mode ................................................... 291
5.3.1 The Receive E3 LIU Interface Block..................................................................................................... 291
Figure 116. The Receive E3 LIU Interface Block .......................................................................................................... 291
Figure 117. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data ............. 292
I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................292
TABLE 56: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE
TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ............................................................. 292
Figure 118. Interfacing the XRT72L52 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU.............................................. 293
Figure 119. Illustration of AMI Line Code...................................................................................................................... 293
Figure 120. Illustration of two examples of HDB3 Decoding......................................................................................... 294
I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................295
TABLE 57: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER, AND THE
SAMPLING EDGE OF THE RXLINECLK SIGNAL ..................................................................................................... 295
Figure 121. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the rising edge of RxLineClk ...................................................................................................... 295
Figure 122. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be
sampled on the falling edge of RxLineClk ..................................................................................................... 296
5.3.2 The Receive E3 Framer Block.............................................................................................................. 296
Figure 123. The Receive E3 Framer Block and the Associated Paths to Other Functional Blocks.............................. 296
Figure 124. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance Algorithm .. 298
Figure 125. Illustration of the E3, ITU-T G.751 Framing Format................................................................................... 298
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ....................................................................299
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11).........................................................300
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ....................................................................300
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ....................................................................300
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11).........................................................301
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52) .....................................301
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53) ......................................301
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11).........................................................302
TABLE 58: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE FRAMING STATE
OF THE RECEIVE E3 FRAMER BLOCK ................................................................................................................ 302
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................303
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11).........................................................303
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ....................................................................303
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) .......................................................................304
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11).........................................................304
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ....................................................................304
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11).........................................................305
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11).........................................................305
RXE3 CONFIGURATION & STATUS REGISTER - 1 G.751 (ADDRESS = 0X10)..............................................305
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ....................................................................306
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11).........................................................306
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11).........................................................306
Figure 126. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote Terminal) with a
correct BIP-4 Value........................................................................................................................................ 307
Figure 127. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote Terminal) with the
A bit set to “0” ................................................................................................................................................ 308
Figure 128. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote Terminal) with an
incorrect BIP-4 value. .................................................................................................................................... 309
Figure 129. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote Terminal) with the
A bit-field set to “1”......................................................................................................................................... 309
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ....................................................................310
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) .......................................................310
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