XR72L52 Datasheet, PDF (244/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
These Receive Section interrupts can be enabled or disabled at the Block Level, by writing the appropriate da-
ta into Bit 7 (Rx DS3/E3 Interrupt Enable) within the Block Interrupt Enable register (Address = 0x04), as illus-
trated below.
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7
RxDS3/E3
Interrupt
Enable
R/W
X
BIT 6
RO
0
BIT 5
BIT 4
Not Used
BIT 3
RO
RO
RO
0
0
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Enable
R/W
0
BIT 0
One Second
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables the Receive Section (at the Block Level) for interrupt generation. Converse-
ly, setting this bit-field to “0” disables the Receive Section for interrupt generation.
4.3.6.2 Enabling/Disabling and Servicing Receive Section Interrupts
The Receive Section of the XRT72L52 Framer IC contains numerous interrupts. The Enabling/Disabling and
Servicing of each of these interrupts is described below.
4.3.6.2.1 The Change of State on Receive LOS Interrupt
If the Change of State on Receive LOS (Loss of Signal) Interrupt is enabled, then the XRT72L52 Framer IC will
generate an interrupt in response to either of the following conditions.
1. When the XRT72L52 Framer IC declares an LOS (Loss of Signal) condition, and
2. When the XRT72L52 Framer IC clears the LOS (Loss of Signal) condition.
Conditions causing the XRT72L52 Framer IC to declare an LOS condition
• If the XRT73L00 LIU IC declares an LOS condition, and drives the RLOS input pin (of the XRT72L52 Framer
IC) "High".
• If the XRT72L52 Framer IC detects a 180 consecutive “0’s”, via the RxPOS and RxNEG input pins and Inter-
nal LOS is enabled, (Address 0x00, bit 5).
Conditions causing the XRT72L52 Framer IC to clear the LOS condition.
• When the XRT73L00 LIU IC ceases declaring an LOS condition and drives the RLOS input pin (of the
XRT72L52 Framer IC) "Low".
• When the XRT72L52 Framer IC detects at least 60 marks (via the RxPOS and RxNEG input pins) out of 180
bit-periods and Internal LOS is enabled, (Address 0x00, bit 5).
Enabling and Disabling the Change of State on Receive LOS Interrupt:
The Change of State on Receive LOS Interrupt can be enabled or disabled by writing the appropriate value into
Bit 6 (LOS Interrupt Enable) within the RxDS3 Interrupt Enable Register, as illustrated below.
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
CP Bit Error
Interrupt
Enable
R/W
0
BIT 6
LOS
Interrupt
Enable
R/W
0
BIT 5
AIS
Interrupt
Enable
R/W
0
BIT 4
Idle Interrupt
Enable
R/W
0
BIT 3
FERF
Interrupt
Enable
R/W
0
BIT 2
AIC
Interrupt
Enable
R/W
0
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Change of State on Receive LOS Interrupt
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