XR72L52 Datasheet, PDF (264/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
TXNSOURCESEL[1:0]
00
01
10
11
SOURCE OF N BIT
TxE3 Service Bits Register (Address = 0x35)
Transmit Overhead Data Input Interface
Transmit LAPD Controller
Transmit Payload Data Input Interface.
FIGURE 89. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L52 TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK AND THE TERMINAL EQUIPMENT (FOR MODE 1 OPERATION)
Terminal Equipment Signals
E3_Clock_In
E3_Data_Out
Tx_Start_of_Frame
E3_Overhead_Ind
Payload[1522] Payload[1523]
FAS, Bit 9
FAS, Bit 8
XRT72L5x Transmit Payload Data I/F Signals
RxOutClk
TxSer
Payload[1522] Payload[1523]
TxFrame
TxOH_Ind
FAS, Bit 9
FAS, Bit 8
E3 Frame Number N
Note: TxFrame pulses high to denote
E3 Frame Boundary.
Note: TxOH_Ind pulses high for
12 bit periods in order to
denote Overhead Data
(e.g., the FAS pattern and the
A & N bits).
E3 Frame Number N + 1
Note: The FAS pattern will not be processed by the
Transmit Payload Data Input Interface.
How to configure the XRT72L52 into the Serial/Loop-Timed/Non-Overhead Interface Mode
1. Set the NibIntf input pin "Low".
2. Set the TimRefSel[1:0] bit fields (within the Framer Operating Mode Register) to "00", as illustrated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
Local
Loop-back
DS3/E3
R/W
R/W
0
0
Internal
LOS
Enable
R/W
1
RESET
R/W
0
Interrupt
Enable
Reset
R/W
1
Frame
Format
R/W
0
3. Interface the XRT72L52, to the Terminal Equipment, as illustrated in Figure 88.
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
0
0
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