XR72L52 Datasheet, PDF (20/480 Pages) Exar Corporation – TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L52
REV. 1.0.1
PIN DESCRIPTION
PIN #
5
PIN NAME
TxLev[0]
6
GND
7
NC
8
TDI
9
TCK
10
NC
11
TRST
12
TMS
13
GND
14
TDO
15
RxOutClk[0]/
RxHDLCDat7[0]
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
TYPE
DESCRIPTION
O Transmit Line Build-Out Enable/Disable Select Output (to be connected to
the XRT73L0x DS3/E3 Line Interface Unit IC):
This output pin is intended to be connected to the TxLev input pin of the
XRT73L0x DS3/E3 Line Interface Unit IC. To control the state of this output pin,
write a "0" or "1" to Bit 2 (TxLev) within the Line Interface Driver Register
(Address = 0x80).
For DS3 Application:
If the user toggleds this signal"High", then the Transmit Line Build-Out circuit
within the XRT73L0x is disabled. In this mode, the XRT73L0x outputs unshaped
(e.g., square) pulses onto the line via the TTIP and TRING output pins.
If the user toggleds this signal "Low", then the Transmit Line Build-Out circuit
within the XRT73L0x is disabled. In this mode, the XRT73L0x outputs shaped
(e.g., more rounded) pulses onto the line via the TTIP and TRING output pins.
In order to comply with the DSX-3 Isolated Pulse Template Requirement per
Bellcore GR-499-CORE, command this output pin to be "High" if the cable
length between the transmit output of the XRT73L0x and the DSX-3 Cross-Con-
nect System is greater than 225 feet. If the cable length is less than 225 feet,
command this output pin to be "Low".
For E3 Applications:
This pin can be used as a General Purpose Output pin. The Transmit Line
Build-Out circuitry within the XRT73L0x is not active for E3 applications.
NOTE: If the XRT73L0x DS3/E3 Line Interface Unit IC is not used, this output
pin may be used for other purposes.
**** Ground
I Test Data In: Boundary Scan Test data input.
I Test Clock: Boundary Scan clock input.
I JTAG Reset Pin: Resets Boundary Scan Logic.
I Test Mode Select: Boundary Scan Mode Select input.
**** Ground
O Test Data Out: Boundary Scan test data output.
O Receive Out Clock - Transmit Terminal Interface Clock for Loop-Timing:
This clock signal functions as the Terminal Interface clock source if the
XRT72L52 Framer is operating in the loop-timing mode.
In this mode, the Transmitting Terminal Equipment is expected to input data to
the Framer, via the TxSer input pin, upon the rising edge of this clock signal. The
XRT72L52 uses the rising edge of this clock signal to sample the data at the
TxSer input.
This clock signal is a buffered version of the RxLineClk signal.
Receive HDLC Data Output - 7:
This pin contains bit 7 RxHDLC data when the HDLC controller is on.
4